This answer record contains the Release Notes and Known Issues for the MIPI CSI-2 Receiver Subsystem and includes the following:
MIPI CSI-2 Receiver Subsystem Page:
https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
General Information
Supported Devices can be found in the following three locations:
For a list of new features and added device support for all versions:
Version Table
This table correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
| Core Version | Vivado Tools Version | IP Changelog | IP Patches |
|---|---|---|---|
| v5.1 (Rev. 3) | 2021.1 | (Xilinx Answer 76541) | |
| v5.1 (Rev. 2) | 2020.3 | -TBA- | |
| v5.1 (Rev. 1) | 2020.2.2 | -TBA- | |
| v5.1 | 2020.2 | (Xilinx Answer 75786) | (Xilinx Answer 76330) |
| v5.0 | 2020.1 | (Xilinx Answer 73626) | (Xilinx Answer 75325) |
| v4.1 | 2019.2 | (Xilinx Answer 72923) | (Xilinx Answer 73100) |
| v4.0 (Rev. 2) | 2019.1.1 | (Xilinx Answer 72494) | |
| v4.0 (Rev. 1) | 2019.1 | (Xilinx Answer 72242) | (Xilinx Answer 75324) |
| v4.0 | 2018.3 | (Xilinx Answer 71806) | (Xilinx Answer 73660) |
| v3.0 (Rev 3) | 2018.2 | (Xilinx Answer 71212) | |
| v3.0 (Rev. 2) | 2018.1 | (Xilinx Answer 70699) | |
| v3.0 (Rev. 1) | 2017.4 | (Xilinx Answer 70386) | |
| v3.0 | 2017.3 | (Xilinx Answer 69903) | |
| v2.2 (Rev. 1) | 2017.2 | (Xilinx Answer 69326) | (Xilinx Answer 69431) |
| v2.2 | 2017.1 | (Xilinx Answer 69055) | |
| v2.1 (Rev. 1) | 2016.4 | (Xilinx Answer 68369) | |
| v2.1 | 2016.3 | (Xilinx Answer 68021) | |
| v2.0 (Rev. 1) | 2016.2 | (Xilinx Answer 67345) | |
| v2.0 | 2016.1 | (Xilinx Answer 66930) | |
| v1.0 | 2015.3 | (Xilinx Answer 65570) |
General Guidance
The table below provides Answer Records for general guidance when using the MIPI CSI-2 Receiver Subsystem.
Table 2: General Guidance
| Article Number | Article Title |
|---|---|
| (Xilinx Answer 76341) | Does the Xilinx MIPI-CSI-2 RX Subsystem support receiving a JPEG stream? |
| (Xilinx Answer 75882) | Migrating MIPI CSI-2 RX Subsystem from ver4.1 (or previous version) to ver5.0 |
| (Xilinx Answer 71582) | MIPI D-PHY RX or MIPI CSI-2 RX Subsystem reporting packet corruptions at higher line-rates |
| (Xilinx Answer 68416) | How do I select different pixel formats for each Virtual Channel in the MIPI CSI-2 RX Subsystem? |
| (Xilinx Answer 70308) | Which licenses are needed to generate the MIPI CSI-2 Application Example Design? |
| (Xilinx Answer 69322) | Why do I get Vivado implementation errors after changing the Calibration Mode to Auto? |
Known and Resolved Issues
The following table provides known issues for the MIPI CSI-2 Receiver Subsystem , starting with v1.0, initially released in Vivado 2015.3.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Table 3: IP
| Article Number | Article Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 76342) | Why can I not build the VCK190 Example design in the 2020.2 release? | v5.1 | (2021.1) |
| (Xilinx Answer 73633) | Why am I failing timing on some -1 parts when trying to set the line rate to 2500Mbps using Vivado 2019.2? | v4.1 | v4.1 |
| (Xilinx Answer 73667) | TUSER port is reporting false CRC, ECC and Frame number | v4.0 | N/A |
| (Xilinx Answer 73373) | MIPI CSI-2 RX Subsystem generated from Vivado 2019.2 does not generate all lines | v4.1 | v5.0 |
| (Xilinx Answer 73099) | IP can generate multiple TLAST and/or TUSER[0] pulses for the first line of each frame with RAW8 and user defined data types | v4.1 | v5.0 |
| (Xilinx Answer 71708) | Unable to synthesize MIPI example design on Windows OS | v3.0 (Rev 3) | v4.0 |
| (Xilinx Answer 69531) | Why do I get the warning "ncelab: *dphy_ip/mipi_dphy.srcs/sources_1/ip/mipi_dphy_rx1/mipi_dphy_rx1_core.v,436|49): implicit wire has no fanin" on system_rst_in when simulating the MIPI DPHY RX? | v2.2 (Rev. 1) | v3.0 |
| (Xilinx Answer 70581) | Why do I see SoT/ECC/CRC errors on MIPI RX IP targeting UltraScale+ devices? | v3.0 (Rev. 1) | v3.0 (Rev. 2) |
| (Xilinx Answer 69441) | Why is the MIPI CSI-2 Receiver with Clock/Data skew calibration set to Auto/Fixed, failing during implementation? | v2.1 (Rev. 1) | v3.0 |
| (Xilinx Answer 69057) | Why is an SOTsynchs error generated from MIPI DPHY RX IP or MIPI CSI-2 Rx Subsystem? | v2.1 (Rev. 1) | v2.2 |
| (Xilinx Answer 67960) | Why do I get a Critical Warning (Vivado 12-1433) when implementing the IP in OOC mode in the Vivado IDE? | v2.1 | N/A |
| (Xilinx Answer 67793) | Why do I see timing failing on the video_aresetn when using two CSI-2 Receiver Subsystems with one as a master and one as a slave? | v2.0 (Rev. 1) | v2.1 |
| (Xilinx Answer 66994) | Why do I get a CRITICAL WARNING about 'vfb_v1_0_2_viv_fifo_gen.v' when instantiating multiple MIPI CSI-2 Receiver Subsystems on my design? | v2.0 | v2.0 (Rev. 1) |
| (Xilinx Answer 65741) | Why do I see [Designutils 20-1280] when opening a design in the Vivado elaboration mode? | v1.0 | v2.0 |
| Article Number | Article Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 69649) | Why do I receive a BSP compilation message saying there is an error in the auto generated xparameters.h file? | v1.1 (Rev. 3) | v2.0 |
| Revision History: | |
|---|---|
| 06/30/2021 | Added IP version up to Vivado 2021.1 |
| 04/02/2021 | Added (Xilinx Answer 76341) and (Xilinx Answer 76330) |
| 12/03/2020 | Added 2020.2 IP version, and (Xilinx Answer 75882) |
| 08/01/2020 | Added Known issue list (Xilinx Answer 73633) |
| 07/01/2020 | Added Known issue list (Xilinx Answer 73667) Added IP patches (Xilinx Answer 73660) (Xilinx Answer 75324)(Xilinx Answer 75325) |
| 02/28/2019 | Added Known issue list (Xilinx Answer 73373) |
| 12/09/2019 | Added IP patches for 2019.2 (Xilinx Answer 73100) (Xilinx Answer 73099) |
| 11/13/2019 | Added IP version up to Vivado 2019.2 to the Version Table |
| 01/18/2019 | Added (Xilinx Answer 71582) to General Guidance Table |
| 01/11/2019 | Added (Xilinx Answer 71708) to Known and Resolved Issues table |
| 04/13/2018 | Added (Xilinx Answer 69469), (Xilinx Answer 68416) and (Xilinx Answer 69531) |
| 04/04/2018 | Added v3.0 (Rev.2) to Version Table and (Xilinx Answer 70581) |
| 03/02/2018 | Added (Xilinx Answer 70308) |
| 02/20/2018 | Added v3.0 and v3.0 (Rev.1) to Version Table. |
| 07/07/2017 | Added (Xilinx Answer 69441). |
| 06/20/2017 | Added v2.2 (Rev.1) to Version Table and (Xilinx Answer 69322). |
| 04/05/2017 | Added v2.1 (Rev.1) and v2.2 to Version Table and (Xilinx Answer 69057). |
| 10/05/2016 | Added v2.0 (Rev.1) and v2.1 to Version Table, (Xilinx Answer 67793) and (Xilinx Answer 67960) . |
| 04/06/2016 | Added v2.0 to Version Table and Added (Xilinx Answer 66994). |
| 10/20/2015 | Added (Xilinx Answer 65741) |
| 09/30/2015 | Initial Release |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 56852 | Xilinx Multimedia, Video and Imaging Solution Center - Top Issues | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 54550 | LogiCORE IP MIPI D-PHY - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions | N/A | N/A |
| 67896 | MIPI CSI-2 Transmitter Subsystem - Release Notes and Known Issues for the Vivado 2016.3 tool and later versions | N/A | N/A |