100M/1G TSN Subsystem (2.0)
Version 2.0 (Rev. 8)
Bug Fix: Added wavers for CDC-11
Bug Fix: Updated (PG275) link in coreinfo
Other: Updated Versal board version on dv file
Revision change in one or more subcores
10G Ethernet MAC (15.1)
Version 15.1 (Rev. 9)
General: Updated CDC waivers
10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)
Version 6.0 (Rev. 19)
General: Added CDC waivers.
Revision change in one or more subcores
10G Ethernet Subsystem (3.1)
Version 3.1 (Rev. 15)
Revision change in one or more subcores
10G/25G Ethernet Subsystem (4.0)
Version 4.0
Feature Enhancement: Added lane selection support in IP Block Automation for Versal board flow
Other: GT serial ports are clubbed for part based design similar to board based design when the new GUI option "Enable GT Interface for Board Based Design" is selected from GT Selection and Configuration Tab
Other: Added for new devices support
Other: Updated the watchdog timer logic to issue gt_rx_reset if link is not up
Revision change in one or more subcores
1G/10G/25G Switching Ethernet Subsystem (2.7)
Version 2.7
Feature Enhancement: Added GTH support for 64-bit variant
Feature Enhancement: Added 1G and 10G only switching support for 64-bit variant
Other: New device support added
Other: Example design constraint provided for better timing results
Revision change in one or more subcores
1G/2.5G Ethernet PCS/PMA or SGMII (16.2)
Version 16.2 (Rev. 4)
Feature Enhancement: Added 156.25 and 312.5 Mhz frequency option to SGMII or 1000BaseX over LVDS for Versal Devices
Feature Enhancement: Added lane selection support to GT Based block automation for Versal devices
Revision change in one or more subcores
32-bit Initiator/Target for PCI (7 Series) (5.0)
Version 5.0 (Rev. 12)
No changes
3GPP LTE Channel Estimator (2.0)
Version 2.0 (Rev. 18)
Revision change in one or more subcores
3GPP LTE MIMO Decoder (3.0)
Version 3.0 (Rev. 16)
No changes
3GPP LTE MIMO Encoder (4.0)
Version 4.0 (Rev. 15)
No changes
3GPP Mixed Mode Turbo Decoder (2.0)
Version 2.0 (Rev. 21)
No changes
3GPP Turbo Encoder (5.0)
Version 5.0 (Rev. 17)
Revision change in one or more subcores
3GPPLTE Turbo Encoder (4.0)
Version 4.0 (Rev. 16)
No changes
40G/50G Ethernet Subsystem (3.2)
Version 3.2 (Rev. 2)
Feature Enhancement: Added lane selection support in IP Block Automation for Versal board flow
Other: Added for new device support
Revision change in one or more subcores
64-bit Initiator/Target for PCI (7 Series) (5.0)
Version 5.0 (Rev. 11)
No changes
7 Series FPGAs Transceivers Wizard (3.6)
Version 3.6 (Rev. 13)
No changes
7 Series Integrated Block for PCI Express (3.3)
Version 3.3 (Rev. 14)
No changes
Accumulator (12.0)
Version 12.0 (Rev. 14)
No changes
ADC DAC Interface IP (1.0)
Version 1.0
No changes
Adder/Subtracter (12.0)
Version 12.0 (Rev. 14)
No changes
Advanced IO Wizard (1.0)
Version 1.0 (Rev. 5)
Feature Enhancement: Timing parameter updates
Feature Enhancement: Advanced Mode
Feature Enhancement: BIDIR State Machine
Feature Enhancement: Data PLL Capture clock updates
Revision change in one or more subcores
AHB-Lite to AXI Bridge (3.0)
Version 3.0 (Rev. 19)
Revision change in one or more subcores
AI Engine (2.0)
Version 2.0 (Rev. 2)
Feature Enhancement: Updating tkeep logic
Revision change in one or more subcores
AMM Master Bridge (1.0)
Version 1.0 (Rev. 10)
Revision change in one or more subcores
AMM Slave Bridge (1.0)
Version 1.0 (Rev. 14)
Revision change in one or more subcores
Audio Clock Recovery Unit (1.0)
Version 1.0 (Rev. 2)
No changes
Audio Formatter (1.0)
Version 1.0 (Rev. 6)
Revision change in one or more subcores
audio_tpg_v1_0 (1.0)
Version 1.0
No changes
aud_pat_gen (1.0)
Version 1.0
No changes
Aurora 64B66B (12.0)
Version 12.0 (Rev. 6)
General: Versal Pre-Production support
Revision change in one or more subcores
Aurora 8B10B (11.1)
Version 11.1 (Rev. 11)
General: Example design constraints updated, no functional changes.
Revision change in one or more subcores
Auto-negotiation and Link Training (1.0)
Version 1.0 (Rev. 3)
Revision change in one or more subcores
AXI 1G/2.5G Ethernet Subsystem (7.2)
Version 7.2 (Rev. 3)
Feature Enhancement: Added SGMII and 1000BaseX over LVDS feature to Versal devices
Feature Enhancement: Added Lane selection support for Versal GT Based block automation flow
Revision change in one or more subcores
AXI AHBLite Bridge (3.0)
Version 3.0 (Rev. 21)
Revision change in one or more subcores
AXI APB Bridge (3.0)
Version 3.0 (Rev. 17)
No changes
AXI BRAM Controller (4.1)
Version 4.1 (Rev. 5)
General: removed Xilinx Internal markings from TLM model sources
AXI Bridge for PCI Express Gen3 Subsystem (3.0)
Version 3.0 (Rev. 17)
Revision change in one or more subcores
AXI CAN (5.0)
Version 5.0 (Rev. 27)
Revision change in one or more subcores
AXI Central Direct Memory Access (4.1)
Version 4.1 (Rev. 24)
Revision change in one or more subcores
AXI Chip2Chip Bridge (5.0)
Version 5.0 (Rev. 12)
Revision change in one or more subcores
AXI Clock Converter (2.1)
Version 2.1 (Rev. 23)
General: removed Xilinx Internal markings from TLM model sources
Revision change in one or more subcores
AXI Crossbar (2.1)
Version 2.1 (Rev. 25)
Feature Enhancement: removed Xilinx Internal markings from TLM model sources
Revision change in one or more subcores
AXI Data FIFO (2.1)
Version 2.1 (Rev. 23)
General: removed Xilinx Internal markings from TLM model sources
Revision change in one or more subcores
AXI Data Width Converter (2.1)
Version 2.1 (Rev. 24)
General: removed Xilinx Internal markings from TLM model sources
Revision change in one or more subcores
AXI DataMover (5.1)
Version 5.1 (Rev. 26)
Revision change in one or more subcores
AXI Direct Memory Access (7.1)
Version 7.1 (Rev. 25)
Revision change in one or more subcores
AXI EMC (3.0)
Version 3.0 (Rev. 24)
Revision change in one or more subcores
AXI EPC (2.0)
Version 2.0 (Rev. 27)
Revision change in one or more subcores
AXI Ethernet Buffer (2.0)
Version 2.0 (Rev. 23)
No changes
AXI Ethernet Clocking (2.0)
Version 2.0 (Rev. 2)
No changes
AXI EthernetLite (3.0)
Version 3.0 (Rev. 23)
Bug Fix: Fixed the TVALID and TLAST generation issue in AXI-Full configuration for the IP
Revision change in one or more subcores
AXI GPIO (2.0)
Version 2.0 (Rev. 26)
Revision change in one or more subcores
AXI HB ICAP (1.0)
Version 1.0 (Rev. 4)
General: No functional change
AXI HWICAP (3.0)
Version 3.0 (Rev. 28)
Revision change in one or more subcores
AXI IIC (2.1)
Version 2.1
General: Fixed RTL to initiate the Read on IIC only after receiving the length in dynamic mode
Revision change in one or more subcores
AXI Interconnect (2.1)
Version 2.1 (Rev. 25)
Revision change in one or more subcores
AXI Interrupt Controller (4.1)
Version 4.1 (Rev. 15)
No changes
AXI Lite IPIF (3.0)
Version 3.0 (Rev. 4)
No changes
AXI Master Burst (2.0)
Version 2.0 (Rev. 7)
No changes
AXI Memory Init (1.0)
Version 1.0 (Rev. 5)
General: update product guide link
Revision change in one or more subcores
AXI Memory Mapped To PCI Express (2.9)
Version 2.9 (Rev. 5)
Revision change in one or more subcores
AXI Memory Mapped to Stream Mapper (1.1)
Version 1.1 (Rev. 23)
Revision change in one or more subcores
AXI MMU (2.1)
Version 2.1 (Rev. 22)
General: Disable Support for Versal
Revision change in one or more subcores
AXI Multi Channel Direct Memory Access (1.1)
Version 1.1 (Rev. 5)
Revision change in one or more subcores
AXI Performance Monitor (5.0)
Version 5.0 (Rev. 26)
Revision change in one or more subcores
AXI Protocol Checker (2.0)
Version 2.0 (Rev. 10)
General: AXI_ERRM_WDATA_NUM check fixed for the case when WLAST arrives late
Revision change in one or more subcores
AXI Protocol Converter (2.1)
Version 2.1 (Rev. 24)
General: removed Xilinx Internal markings from TLM model sources
Revision change in one or more subcores
AXI Protocol Firewall (1.1)
Version 1.1 (Rev. 3)
Revision change in one or more subcores
AXI Quad SPI (3.2)
Version 3.2 (Rev. 23)
General: CR Fixes
Revision change in one or more subcores
AXI Register Slice (2.1)
Version 2.1 (Rev. 24)
General: removed Xilinx Internal markings from TLM model sources
Revision change in one or more subcores
AXI Remapper IP for Rx (1.0)
Version 1.0
No changes
AXI Remapper IP for Tx (1.0)
Version 1.0
No changes
AXI Sideband Utility (1.0)
Version 1.0 (Rev. 8)
Revision change in one or more subcores
AXI SmartConnect (1.0)
Version 1.0 (Rev. 16)
Feature Enhancement: Enhanced low area mode automation to support cascaded SI and MI when all reachable slave endpoints are AXI4Lite 32-bit
Feature Enhancement: Enhanced low area mode automation to support 32-bit AXI4/AXI3 endpoint slaves when all SI connect to AXI4Lite 32-bit masters
Feature Enhancement: Allow non-power-of-2 values for segment range
Feature Enhancement: Reduced AXI4 Area mode (experimental, undocumented) when no width-conv and no clock-conv among all SC interfaces; guarded by 'set_property -dict [list CONFIG.ADVANCED_PROPERTIES {__experimental_features__ {reduced_axi4_area_mode 1}}]'.
Revision change in one or more subcores
AXI TFT Controller (2.0)
Version 2.0 (Rev. 23)
No changes
AXI Timebase Watchdog Timer (3.0)
Version 3.0 (Rev. 16)
Revision change in one or more subcores
AXI Timer (2.0)
Version 2.0 (Rev. 26)
Revision change in one or more subcores
AXI Traffic Generator (3.0)
Version 3.0 (Rev. 10)
General: No functional changes
Revision change in one or more subcores
AXI UART16550 (2.0)
Version 2.0 (Rev. 26)
Revision change in one or more subcores
AXI Uartlite (2.0)
Version 2.0 (Rev. 28)
Revision change in one or more subcores
AXI USB2 Device (5.0)
Version 5.0 (Rev. 25)
Revision change in one or more subcores
AXI Verification IP (1.1)
Version 1.1 (Rev. 10)
General: added external process traffic generation support using XTLM IPC for SystemC Models
Revision change in one or more subcores
AXI Video Direct Memory Access (6.3)
Version 6.3 (Rev. 12)
Revision change in one or more subcores
AXI Virtual FIFO Controller (2.0)
Version 2.0 (Rev. 26)
Revision change in one or more subcores
AXI-Stream FIFO (4.2)
Version 4.2 (Rev. 6)
Revision change in one or more subcores
AXI4 Debug Hub (2.0)
Version 2.0 (Rev. 1)
General: Updated the device support for Versal devices to Production
AXI4-Stream Accelerator Adapter (2.1)
Version 2.1 (Rev. 16)
No changes
AXI4-Stream Broadcaster (1.1)
Version 1.1 (Rev. 23)
Revision change in one or more subcores
AXI4-Stream Clock Converter (1.1)
Version 1.1 (Rev. 25)
Revision change in one or more subcores
AXI4-Stream Combiner (1.1)
Version 1.1 (Rev. 22)
Revision change in one or more subcores
AXI4-Stream Data FIFO (2.0)
Version 2.0 (Rev. 6)
General: Modified aclken pins to ACTIVE HIGH when used in IPI
Revision change in one or more subcores
AXI4-Stream Data Width Converter (1.1)
Version 1.1 (Rev. 23)
General: Removed TLM models
Revision change in one or more subcores
AXI4-Stream Interconnect (2.1)
Version 2.1 (Rev. 25)
Revision change in one or more subcores
AXI4-Stream Protocol Checker (2.0)
Version 2.0 (Rev. 8)
Revision change in one or more subcores
AXI4-Stream Register Slice (1.1)
Version 1.1 (Rev. 24)
Revision change in one or more subcores
AXI4-Stream Subset Converter (1.1)
Version 1.1 (Rev. 24)
Revision change in one or more subcores
AXI4-Stream Switch (1.1)
Version 1.1 (Rev. 24)
Revision change in one or more subcores
AXI4-Stream to Video Out (4.0)
Version 4.0 (Rev. 12)
General: Support for framebuffer-less passthrough system in adaptive sync mode by inhibiting FIFO reads until SOF from VTC and by inhibiting FIFO writes until SOF from AXI4S
AXI4-Stream Verification IP (1.1)
Version 1.1 (Rev. 10)
Revision change in one or more subcores
axi_msg (1.0)
Version 1.0 (Rev. 6)
No changes
axi_sg (4.1)
Version 4.1 (Rev. 13)
No changes
Binary Counter (12.0)
Version 12.0 (Rev. 14)
No changes
Block Memory Generator (8.4)
Version 8.4 (Rev. 4)
No changes
BUFG GT (1.0)
Version 1.0 (Rev. 4)
General: Added support for additional devices with GTYP and GTM
CAM IP (2.2)
Version 2.2
New Feature: Supporting entry of DEFAULT_RESPONSE Value
New Feature: Added support for Debug Flags: CAM_DEBUG_CONFIG_ARGS & CAM_DEBUG_SET_COVER
New Feature: Dump Memory feature added, usage details available in example design
New Feature: New AXI-Stream response flag for lookup ECC double-bit errors, located after the MatchFlag
New Feature: The sbiterr/dbiterr outputs, ECC counters, ECC address registers are updated during scrubbing only
New Feature: New software function for calculation of driver heap size requirements
Other: Internal versions (H/W = 2.20; S/W = 2.20)
CANFD (3.0)
Version 3.0 (Rev. 3)
General: Can clock removed from can interface as it is already modeled as a separate clock interface.
Revision change in one or more subcores
Card Management Solution Subsystem (4.0)
Version 4.0
General: Standard in-band card management features now supported for all supported cards
General: Mailbox function QSFP IIC block write deprecated
General: Example Design now uses selected part rather than board part
Revision change in one or more subcores
CIC Compiler (4.0)
Version 4.0 (Rev. 15)
No changes
Clock Verification IP (1.0)
Version 1.0 (Rev. 2)
No changes
Clocking Wizard (1.0)
Version 1.0 (Rev. 6)
General: CR Fixes.
Clocking Wizard (6.0)
Version 6.0 (Rev. 8)
Bug Fix: Internal GUI fixes
Other: CR Fixes
Compact GT (1.0)
Version 1.0 (Rev. 9)
Revision change in one or more subcores
Complex Multiplier (6.0)
Version 6.0 (Rev. 20)
General: removal of forced SRL inference for small delays. Performance and resources might be affected.
Revision change in one or more subcores
Concat (2.1)
Version 2.1 (Rev. 4)
No changes
Constant (1.1)
Version 1.1 (Rev. 7)
No changes
Control, Interfaces & Processing System (3.0)
Version 3.0 (Rev. 1)
General: Change log available at (Xilinx Answer 76535)
Revision change in one or more subcores
Convolution Encoder (9.0)
Version 9.0 (Rev. 15)
No changes
CORDIC (6.0)
Version 6.0 (Rev. 17)
Revision change in one or more subcores
CPRI (8.11)
Version 8.11 (Rev. 7)
Bug Fix: Fixed a bug with nodebfn_tx_strobe alignment if the strobe was in advance of iq_tx_enable by 2 clock cycles.
Bug Fix: Fixed a bug in 0.614Gb/s line rate 64bit datapath which caused an intermittent failure to reach the operate state.
Bug Fix: Fixed a bug in the example design when the Hard FEC option is selected with shared logic in the example design. The error only occurs in devices with both GTH and GTY transceivers. No change to core.
Bug Fix: Fixed a bug in the Versal example design when the RT Vendor Support option is enabled. The example design data checker module was reporting RT Vendor data errors. No change to core.
Feature Enhancement: For Versal designs added extended CDC FIFO Depth option to the GUI.
Other: Updated to use v1.1 of the Versal gt_quad_base.
Revision change in one or more subcores
DDR3 SDRAM (MIG) (1.4)
Version 1.4 (Rev. 12)
General: No Updates
Revision change in one or more subcores
DDR4 SDRAM (MIG) (2.2)
Version 2.2 (Rev. 12)
General: No Updates
Revision change in one or more subcores
DDS Compiler (6.0)
Version 6.0 (Rev. 21)
Revision change in one or more subcores
Debug Bridge (3.0)
Version 3.0 (Rev. 6)
No changes
Debug Interface Module (1.0)
Version 1.0
No changes
DFE Channel Filter (1.0)
Version 1.0
General: Initial release
DFE DUC-DDC Mixer (1.0)
Version 1.0
General: Initial release
DFE Equalizer Filter (1.0)
Version 1.0
General: Initial release
DFE FFT (1.0)
Version 1.0
General: Initial release
DFE PRACH (1.0)
Version 1.0
General: Initial release
DFE Resampler (1.0)
Version 1.0
General: Initial release
DFX AXI Shutdown Manager (1.0)
Version 1.0
No changes
DFX Bitstream Monitor (1.0)
Version 1.0
No changes
DFX Controller (1.0)
Version 1.0 (Rev. 1)
No changes
DFX Decoupler (1.0)
Version 1.0 (Rev. 2)
General: Added SystemC emulation model
General: Minor change to IPI propagation implementation.
Discrete Fourier Transform (4.2)
Version 4.2 (Rev. 2)
Bug Fix: Fixed power-on edge case
Bug Fix: Fixed stale C model file which was causing issues in shared object file
DisplayPort (9.0)
Version 9.0 (Rev. 3)
No changes
DisplayPort RX Subsystem (2.1)
Version 2.1 (Rev. 11)
Bug Fix: Removed GTYE4 device support. Users should use DP 1.4 Subsystem for GTYE4 support
Feature Enhancement: AXI IIC update in example design Tcl scripts
Revision change in one or more subcores
DisplayPort TX Subsystem (2.1)
Version 2.1 (Rev. 11)
Bug Fix: Removed GTYE4 device support. Users should use DP 1.4 Subsystem for GTYE4 support
Revision change in one or more subcores
Distributed Memory Generator (8.0)
Version 8.0 (Rev. 13)
No changes
Divider Generator (5.1)
Version 5.1 (Rev. 18)
Revision change in one or more subcores
DMA/Bridge Subsystem for PCI Express (4.1)
Version 4.1 (Rev. 12)
General: Added xcux35,vu19p_CIV,vu31p_CIV and vu45p_CIV device support.
Revision change in one or more subcores
Double Data Rate Sampling (1.0)
Version 1.0
No changes
DP DSC AXI4-Stream to Video Out (1.0)
Version 1.0 (Rev. 2)
Revision change in one or more subcores
DSP Macro (1.0)
Version 1.0 (Rev. 2)
Bug Fix: Automatic upgrade from dsp48_macro_v3_0 now that it is discontinued.
Bug Fix: Errors correctly flagged for validation of instruction list via cmd line.
DUC/DDC Compiler (3.0)
Version 3.0 (Rev. 15)
No changes
ECC (2.0)
Version 2.0 (Rev. 13)
No changes
ERNIC (3.1)
Version 3.1
General: resource optimization and pfc Feature addition
ETRNIC (1.1)
Version 1.1 (Rev. 3)
No changes
Fast Adapter (1.0)
Version 1.0 (Rev. 1)
Revision change in one or more subcores
Fast Fourier Transform (9.1)
Version 9.1 (Rev. 6)
Revision change in one or more subcores
FEC 5G Common Utilities (1.1)
Version 1.1 (Rev. 1)
No changes
Fibre Channel 32GFC RS-FEC (1.0)
Version 1.0 (Rev. 18)
General: Support latest Versal devices.
Revision change in one or more subcores
FIFO Generator (13.2)
Version 13.2 (Rev. 5)
No changes
FIR Compiler (7.2)
Version 7.2 (Rev. 16)
Bug Fix: Fixed width mismatch issue with SSR single rate extended multiply reload configs
Other: testbench and constraints updates
Fixed Interval Timer (2.0)
Version 2.0 (Rev. 10)
No changes
FlexO 100G RS-FEC (1.0)
Version 1.0 (Rev. 18)
General: Support latest Versal devices.
Revision change in one or more subcores
Floating-point (7.1)
Version 7.1 (Rev. 12)
General: Cosmetic internal changes. No change to functionality.
Revision change in one or more subcores
G.709 FEC Encoder/Decoder (2.4)
Version 2.4 (Rev. 3)
Bug Fix: correction to demo_tb pkg for Riviera. No effect on other simulators, performance or function.
G.975.1 EFEC I.4 Encoder/Decoder (1.0)
Version 1.0 (Rev. 18)
No changes
G.975.1 EFEC I.7 Encoder/Decoder (2.0)
Version 2.0 (Rev. 18)
No changes
Gamma LUT (1.1)
Version 1.1 (Rev. 2)
General: Added Versal example design support
Revision change in one or more subcores
GMII to RGMII (4.1)
Version 4.1 (Rev. 2)
Bug Fix: Updated common.tcl for new Versal device and some syntax error removed.
Other: Adding support for Versal New device
gtm_cntrl (1.0)
Version 1.0 (Rev. 8)
Revision change in one or more subcores
gt_soft_helper (1.0)
Version 1.0
Feature Enhancement: Initial version
gt_subcore_ip_v1_0 (1.0)
Version 1.0 (Rev. 4)
General: Added new transceiver configuration preset options for GTYP and GTM
HBM IP (1.0)
Version 1.0 (Rev. 11)
General: Supported Post-Synth / Post-Implementation Netlist Simulation
General: Refresh Period Temperature Compensation GUI option is enabled by default
General: Supported vu31p_CIV and vu45p_CIV devices.
HDCP (1.0)
Version 1.0 (Rev. 3)
No changes
HDCP 2.2 Cipher (1.0)
Version 1.0 (Rev. 3)
No changes
HDCP 2.2 Cipher for DP (1.0)
Version 1.0
No changes
HDCP 2.2 Montgomery Modular Multiplier (1.0)
Version 1.0 (Rev. 2)
No changes
HDCP 2.2 Random Number Generator (1.0)
Version 1.0 (Rev. 1)
No changes
HDCP 2.2 Receiver (1.0)
Version 1.0 (Rev. 16)
Revision change in one or more subcores
HDCP 2.2 Receiver for DisplayPort 1.4 Subsystems (1.0)
Version 1.0 (Rev. 5)
Revision change in one or more subcores
HDCP 2.2 Transmitter (1.0)
Version 1.0 (Rev. 16)
Revision change in one or more subcores
HDCP 2.2 Transmitter for DisplayPort 1.4 Subsystem (1.0)
Version 1.0 (Rev. 5)
Revision change in one or more subcores
HDMI 1.4/2.0 Receiver (3.0)
Version 1.1
No changes
HDMI 1.4/2.0 Receiver Subsystem (3.2)
Version 3.2
Bug Fix: Native Video Bus Interface name is changed from VIDEO_OUT to NATIVE_VID_OUT
Bug Fix: ZCU104 example design FSBL loading issue
Feature Enhancement: Vsync and Hsync Alignment check is relaxed for progressive to support older sources
Revision change in one or more subcores
HDMI 1.4/2.0 Transmitter (3.0)
Version 2.0
No changes
HDMI 1.4/2.0 Transmitter Subsystem (3.2)
Version 3.2
Bug Fix: Native Video Bus Interface name is changed from VIDEO_IN to NATIVE_VID_IN
Bug Fix: ZCU104 example design FSBL loading issue
Revision change in one or more subcores
HDMI 2.0/2.1 Receiver (1.0)
Version 1.0 (Rev. 1)
Revision change in one or more subcores
HDMI 2.0/2.1 Transmitter (1.0)
Version 1.0 (Rev. 1)
Revision change in one or more subcores
HDMI 2.1 Receiver Subsystem (1.2)
Version 1.2
Bug Fix: Native Video Bus Interface name is changed from VIDEO_OUT to NATIVE_VID_OUT
Bug Fix: CDC-1 CW reported on DDC lines
Feature Enhancement: Support for Dynamic HDR
Feature Enhancement: Support for Enhanced Gaming & Media Feature (VRR,FVA,QMS,ALLM)
Revision change in one or more subcores
HDMI 2.1 Transmitter Subsystem (1.2)
Version 1.2
Bug Fix: Native Video Bus Interface name is changed from VIDEO_IN to NATIVE_VID_IN
Bug Fix: CDC-1 CW reported on DDC lines
Feature Enhancement: Support for Dynamic HDR
Feature Enhancement: Support for Enhanced Gaming & Media Feature(VRR,FVA,QMS,ALLM)
Revision change in one or more subcores
HDMI GT Controller (1.0)
Version 1.0 (Rev. 5)
General: Updates to source the GT parameters from latest gt_quad_base
Revision change in one or more subcores
HDMI PHY Controller (1.0)
Version 1.0 (Rev. 3)
General: Added Max Line Rates for virtexuplusHBM and virtexuplus58g family devices
Revision change in one or more subcores
HDMI_ACR_CTRL (1.0)
Version 1.0
No changes
High Speed SelectIO Wizard (3.6)
Version 3.6 (Rev. 1)
No changes
I2S Receiver (1.0)
Version 1.0 (Rev. 5)
No changes
I2S Transmitter (1.0)
Version 1.0 (Rev. 5)
No changes
IBERT 7 Series GTH (3.0)
Version 3.0 (Rev. 18)
No changes
IBERT 7 Series GTP (3.0)
Version 3.0 (Rev. 19)
General: Updated example design script to use respective implementation strategy to fix timing issue.
IBERT 7 Series GTX (3.0)
Version 3.0 (Rev. 18)
No changes
IBERT 7 Series GTZ (3.1)
Version 3.1 (Rev. 19)
General: Updated the placement constraints for the core
IBERT UltraScale GTH (1.4)
Version 1.4 (Rev. 6)
Revision change in one or more subcores
IBERT UltraScale GTM (1.0)
Version 1.0 (Rev. 11)
Bug Fix: Updated revision number of include file
Revision change in one or more subcores
IBERT UltraScale GTY (1.3)
Version 1.3 (Rev. 6)
Feature Enhancement: Adding IBERT support for two channel quads for vu23p devices
Revision change in one or more subcores
IEEE 802.3 200G RS-FEC (2.0)
Version 2.0 (Rev. 2)
Bug Fix: Fix GTM-based hard FEC reliability issues.
Other: Support latest Versal parts.
Revision change in one or more subcores
IEEE 802.3 25G RS-FEC (1.0)
Version 1.0 (Rev. 20)
General: Support latest Versal parts.
Revision change in one or more subcores
IEEE 802.3 400G RS-FEC (2.0)
Version 2.0 (Rev. 4)
Bug Fix: Fix GTM-based hard FEC reliability issues.
Other: Support added for latest Versal parts.
Revision change in one or more subcores
IEEE 802.3 50G RS-FEC (2.0)
Version 2.0 (Rev. 8)
General: Support latest Versal parts.
Revision change in one or more subcores
IEEE 802.3 Clause 74 FEC (1.0)
Version 1.0 (Rev. 10)
General: Support added for latest Versal devices.
Revision change in one or more subcores
IEEE 802.3 Multi-channel 25G RSFEC (1.0)
Version 1.0 (Rev. 13)
General: Updated device support
General: Added fec_enable pins for each channel
Revision change in one or more subcores
IEEE 802.3bj 100G RS-FEC (2.0)
Version 2.0 (Rev. 12)
General: Supports latest Versal parts.
Revision change in one or more subcores
ILA (Integrated Logic Analyzer with AXIS Interface) (1.1)
Version 1.1 (Rev. 3)
Feature Enhancement: Fixed timing
Revision change in one or more subcores
ILA (Integrated Logic Analyzer) (6.2)
Version 6.2 (Rev. 11)
No changes
In System IBERT (1.0)
Version 1.0 (Rev. 13)
Revision change in one or more subcores
Interlaken 150G (2.4)
Version 2.4 (Rev. 8)
General: Added new device support
Revision change in one or more subcores
Interleaver/De-interleaver (8.0)
Version 8.0 (Rev. 16)
Revision change in one or more subcores
interrupt_controller (3.1)
Version 3.1 (Rev. 4)
No changes
IOModule (3.1)
Version 3.1 (Rev. 7)
General: Updated to avoid issue in Questa behavioral simulation, no functional changes
JESD204 (7.2)
Version 7.2 (Rev. 12)
General: UltraScale and UltraScale+ families are no longer supported in JESD204B, which has been superseded in 2021.1 by the JESD204C IP core.
Revision change in one or more subcores
JESD204 PHY (4.0)
Version 4.0 (Rev. 12)
Bug Fix: Previously unconnected GT Common input signal common_qpll0_reset is tied off low when qpll0 is not in use.
Other: NA
Revision change in one or more subcores
JESD204C (4.2)
Version 4.2 (Rev. 5)
Bug Fix: Fix to correct FEC mode operation.
Other: Updated to use v1.1 of the Versal gt_quad_base.
Other: Removed the upper limit of 32.0Gb/s line rate on JESD204C, the upper limit is now defined by the GT max line rate.
Revision change in one or more subcores
JTAG to AXI Master (1.2)
Version 1.2 (Rev. 13)
Revision change in one or more subcores
LDPC Encoder/Decoder (2.0)
Version 2.0 (Rev. 8)
Bug Fix: Correction to example design helper IP driver Makefiles to support Windows tool chain.
Bug Fix: Correction to example design board support.
Other: Refreshed example design helper IP for latest tool compatibility and associated example design changes.
lib_bmg (1.0)
Version 1.0 (Rev. 13)
No changes
lib_cdc (1.0)
Version 1.0 (Rev. 2)
No changes
lib_fifo (1.0)
Version 1.0 (Rev. 14)
No changes
lib_pkg (1.0)
Version 1.0 (Rev. 2)
No changes
lib_srl_fifo (1.0)
Version 1.0 (Rev. 2)
No changes
LMB BRAM Controller (4.0)
Version 4.0 (Rev. 19)
No changes
Local Memory Bus (LMB) 1.0 (3.0)
Version 3.0 (Rev. 11)
No changes
Lossless Compression (1.0)
Version 1.0
No changes
LPDDR3 SDRAM (MIG) (1.0)
Version 1.0 (Rev. 12)
General: No Updates
Revision change in one or more subcores
LTE DL Channel Encoder (4.0)
Version 4.0 (Rev. 3)
Revision change in one or more subcores
LTE Fast Fourier Transform (2.1)
Version 2.1 (Rev. 4)
Bug Fix: removal of superfluous debug statements in c model
Bug Fix: update of error trap in MEX which prevented use of new point sizes
Bug Fix: correction to cp_val interface enablement
Revision change in one or more subcores
LTE PUCCH Receiver (2.0)
Version 2.0 (Rev. 19)
Revision change in one or more subcores
LTE RACH Detector (3.1)
Version 3.1 (Rev. 9)
Revision change in one or more subcores
LTE UL Channel Decoder (4.0)
Version 4.0 (Rev. 17)
No changes
Mailbox (2.1)
Version 2.1 (Rev. 14)
No changes
Mammoth Transcoder (1.0)
Version 1.0
No changes
Maxwell Reference Common Core (1.0)
Version 1.0
Initial release
Memory Helper Core (1.4)
Version 1.4
No changes
Memory Interface Generator (MIG 7 Series) (4.2)
Version 4.2 (Rev. 1)
No changes
MicroBlaze (11.0)
Version 11.0 (Rev. 6)
General: Added reset on flip-flops, no functional changes
General: Avoid address segment warning
General: Renamed "Resources" to "Resource Estimates" in the configuration dialog to distinguish it from "Resources" provided by Vivado
MicroBlaze Debug Module (MDM) (3.2)
Version 3.2 (Rev. 21)
General: Added clock constraint and waivers for Versal ACAP ES1 devices.
MicroBlaze MCS (3.0)
Version 3.0 (Rev. 16)
Feature Enhancement: Added optimization that excludes hardware multiplier
Other: Improve upgrade to ensure that interfaces are not disabled
Revision change in one or more subcores
MIPI CSI-2 Rx Controller (1.0)
Version 1.0 (Rev. 8)
No changes
MIPI CSI-2 Rx Subsystem (5.1)
Version 5.1 (Rev. 3)
Bug Fix: Fixed VCK190 example design generation issue
Bug Fix: Fixed SP701 example design SW application to get proper colors
Bug Fix: Fixed buffer full condition(ISR[18]) issues for line rates > 1500
Feature Enhancement: IDELAY Tap Value setting in Fixed calibration mode using external ports for 7 Series devices
Feature Enhancement: Example design instance names reduced to support generation using Windows OS
Revision change in one or more subcores
MIPI CSI-2 Tx Controller (1.0)
Version 1.0 (Rev. 4)
No changes
MIPI CSI-2 Tx Subsystem (2.2)
Version 2.2 (Rev. 2)
Bug Fix: Fixed clock, data misalignment issue in Master mode for Versal families
Feature Enhancement: Added YUV 422 10bit support
Revision change in one or more subcores
MIPI D-PHY (4.3)
Version 4.3 (Rev. 2)
Bug Fix: Fixed clock, data misalignment issue in Master mode for Versal families
Feature Enhancement: IDELAY Tap Value setting in Fixed calibration mode using external ports for 7 Series devices
Revision change in one or more subcores
MIPI DSI Tx Controller (1.0)
Version 1.0 (Rev. 7)
No changes
MIPI DSI Tx Subsystem (2.2)
Version 2.2 (Rev. 2)
Bug Fix: Fixed clock, data misalignment issue in Master mode for Versal families
Revision change in one or more subcores
Multiplier (12.0)
Version 12.0 (Rev. 17)
General: removal of forced SRL inference for small delays. Performance and resources might be affected.
Multiply Adder (3.0)
Version 3.0 (Rev. 16)
Revision change in one or more subcores
Mutex (2.1)
Version 2.1 (Rev. 11)
No changes
NoC Clock Re-Convergent Buffer (1.0)
Version 1.0
No changes
NoC NIDB (1.0)
Version 1.0
No changes
NoC Packet Repeater (1.0)
Version 1.0
No changes
NoC Packet Switch (1.0)
Version 1.0
No changes
NVMe Host Accelerator (1.0)
Version 1.0 (Rev. 5)
General: Versal Device support added
Revision change in one or more subcores
NVMe Target Controller (2.0)
Version 2.0 (Rev. 2)
General: Versal Device Support Added
Revision change in one or more subcores
ORAN Radio IF (2.0)
Version 2.0
Bug Fix: Fixed issue where data could enter the circular buffer before the Filter was configured
Bug Fix: Fixed issue on UL Seq ID incrementing by more than 1 for a given RTCID/PCID
Bug Fix: Fixed cc_enable routing to DL data path. CC reconfiguration could result in a small burst of data from the PDxCH port.
Bug Fix: Fixed issues causing timing violations in the packet filter as well as in the circular buffer
Bug Fix: Fixed issue in the reception window block causing confusion between late and early packets
Bug Fix: Fixed issue in the performance counters causing the appearance of dummy control packets and partially wrong register reads
Bug Fix: Fixed issue preventing the UL packet generator from using the frameId provided in the correspondent C-Plane message
Bug Fix: Fixed issue in PUxCH preventing application layer fragmentation, when C-Plane specifies numPrb=0, or when the number of RBs give a section size is greater maximum size allowed for each Ethernet packet
Bug Fix: Fixed issue where assertion of tvalid, before tready on the 1st beat of a symbol (DL data), skips the first word.
Bug Fix: Fixed Tready/Tvalid pushback issues on the eBID ports
Bug Fix: Fixed Tready/Tvalid pushback issues on the processor message ports
Bug Fix: Fixed BFP compressed RB size issue on DL data pipe
Bug Fix: Fixed issue preventing correct generation of Early BIDs when only a subset of configured Spatial Streams are actually receiving packets
Bug Fix: Fixed issue generating wrong or missing UL data packets after the input FIFO has become full for a while
Bug Fix: Fixed issues with greater that 255 rb calculation for numPrb 0
Bug Fix: Fixed issue with Extension 1 on Section Type 3 messages
Bug Fix: Fixed UL no request response. FIFO level not reset on rollover clear signal, blocking UL traffic.
Bug Fix: Fixed issue preventing the core from accepting padded control packets which have been tagged by a network switch, resulting in a 68 octet frame
Bug Fix: Fixed generation of udCompHdr parameter extracted from uplink Application Layer on parser port
Bug Fix: Fixed issue causing repetition of data on U-Plane data ports when packets are arriving close to the end of the reception window
Bug Fix: Fixed malfunction of the parser when there is more than one concatenated extension
Bug Fix: Fixed reception window checking for PRACH control packets
Bug Fix: Fixed replication on uplink U-Plane packets of the FrameId held in the correspondent control message
Bug Fix: Additional registers placed on reset paths to ease fanout and replication.
Feature Enhancement: Add support for numPrb greater than 1 for PRACH channel(used for repetition).
Feature Enhancement: Introduced support for DL Section Type3 messages, thus propagating time and frequency offset up to the beamId forward interfaces/xorif_prach_if
Feature Enhancement: Introduced capability to flush the UL request table at the end of each symbol period thus dropping any unanswered request
Feature Enhancement: Max Ethernet packet size increased to 16000 bytes. Enables support for 9600 byte jumbo frames and use of the buffer for a small amount of backpressure
Feature Enhancement: Introduced buffer on each Eth_Port pipeline to store Extension Type 3 information and feed an external LTE precoding block through a single interface
Feature Enhancement: Introduced support for Dynamic definition of the compression method and width to be applied to U-Plane UL data messages
Feature Enhancement: Introduced initial Static BFP 12 and 9 support on all PUxCH interfaces
Feature Enhancement: Introduced initial Static BFP 12 and 9 support on all PDxCH interfaces
Feature Enhancement: Introduced support for Section Type0 messages, adding a signal to switch off the radio
Feature Enhancement: Made it possible to advance the time when the Uplink Beam ID Forward interface is generated to ease the beam former operations
Feature Enhancement: Introduced support for Section Extension messages 4 and 5 for Modulation decompression + bit unpacking on the PDxCH interface.
Feature Enhancement: Increase the number of PDxCH interfaces to 20
Feature Enhancement: Included startprb and numprb associated to each Beam ID in the Early Beam ID interface
Other: Eth RX FIFO removed from Example System
Other: Added NOOP support to the TX PTP logic in the Example System
Other: Reworked example design to use xorif API call function names
Partial Reconfiguration Decoupler (1.0)
Version 1.0 (Rev. 10)
General: Updated to be hidden and only useable by appcores
PCIe AXI4-Lite_Tap (1.0)
Version 1.0 (Rev. 1)
No changes
Peak Cancellation Crest Factor Reduction (6.4)
Version 6.4 (Rev. 2)
Bug Fix: Latency formulae update for TUSER delay against PC-CFR Cosimulation framework
Bug Fix: MIF Size readback value correct as per pg097
Platform Shell Address Remapper (1.0)
Version 1.0 (Rev. 3)
Revision change in one or more subcores
Polar Encoder/Decoder (1.0)
Version 1.0 (Rev. 8)
Bug Fix: Correction to example design helper IP driver Makefiles to support Windows tool chain.
Other: Refreshed example design helper IP for latest tool compatibility and associated example design changes.
Processor System Reset (5.0)
Version 5.0 (Rev. 13)
No changes
PTP 1588 Timer and Syncer (2.0)
Version 2.0
Unknown category others: Reg map changed
Unknown category others: New function added for auto refresh
Unknown category others: New function added for snapshot on external PPS pulse
Unknown category others: Offset register added for port timers
Unknown category others: MRMAC MODE parameter removed
Unknown category others: Sys timer period adjustment register added
QDRII+ SRAM (MIG) (1.4)
Version 1.4 (Rev. 14)
General: No Updates
Revision change in one or more subcores
QDRIV SRAM (MIG) (2.0)
Version 2.0 (Rev. 12)
General: No Updates
Revision change in one or more subcores
QDRIV SRAM PHY IP (2.0)
Version 1.2
No changes
QSGMII (3.5)
Version 3.5 (Rev. 3)
Feature Enhancement: Added for new device support
Revision change in one or more subcores
Queue DMA Subsystem for PCI Express (4.0)
Version 4.0 (Rev. 6)
General: Added xcux35,vu19p_CIV,31p_CIV && 45p_CIV device support
General: Removed Tandem support for RFSoC devices
Revision change in one or more subcores
Radio over Ethernet Framer (3.0)
Version 3.0 (Rev. 2)
Bug Fix: None
Feature Enhancement: None
Other: Removed 2018 work-arounds from Example System (Exs)
Other: Updated Example Design (Exd) for external radio source simulation
Other: Added NOOP support to the TX PTP logic in the Example System (Exs)
RAM-based Shift Register (12.0)
Version 12.0 (Rev. 14)
No changes
RAMA IP (1.1)
Version 1.1 (Rev. 10)
General: Update example design (for timing estimation) - corrected resets to remove warnings
Revision change in one or more subcores
Reed-Solomon Decoder (9.0)
Version 9.0 (Rev. 17)
No changes
Reed-Solomon Encoder (9.0)
Version 9.0 (Rev. 16)
No changes
Reset Verification IP (1.0)
Version 1.0 (Rev. 4)
No changes
RLDRAM3 (MIG) (1.4)
Version 1.4 (Rev. 12)
General: No Updates
Revision change in one or more subcores
RTL Kernel Wizard (1.0)
Version 1.0 (Rev. 4)
Bug Fix: Remove AXI Lite Control interface with ap_ctrl_none and 0 scalar variables
New Feature: Allow scalar variables to always be independent of the kernel control type
Revision change in one or more subcores
SC EXIT (1.0)
Version 1.0 (Rev. 11)
No changes
SC MMU (1.0)
Version 1.0 (Rev. 10)
No changes
SC SI_CONVERTER (1.0)
Version 1.0 (Rev. 10)
No changes
SC SPLITTER (1.0)
Version 1.0 (Rev. 4)
No changes
SC TRANSACTION_REGULATOR (1.0)
Version 1.0 (Rev. 9)
No changes
SDI RX to Video Bridge (2.0)
Version 2.0
No changes
SelectIO Interface Wizard (5.1)
Version 5.1 (Rev. 16)
General: Internal bug fixes.
Sensor Demosaic (1.1)
Version 1.1 (Rev. 2)
General: CHANGELOG:Missing change descriptions
Revision change in one or more subcores
Serial RapidIO Gen2 (4.1)
Version 4.1 (Rev. 11)
General: Forced init reference logic to be added in comments of example design logic. No functional changes
Revision change in one or more subcores
Shell Card Management Controller Subsystem (2.2)
Version 1.0 (Rev. 4)
Revision change in one or more subcores
Shell Utility Build Info (1.0)
Version 1.0
No changes
Shell Utility MSP432 BSL CRC Generator (1.0)
Version 1.0
No changes
Slice (1.0)
Version 1.0 (Rev. 2)
No changes
SmartConnect AXI2SC Bridge (1.0)
Version 1.0 (Rev. 7)
No changes
SmartConnect NOC Entry Bridge (1.0)
Version 1.0
No changes
SmartConnect NOC Exit Bridge (1.0)
Version 1.0
No changes
SmartConnect NOC Router (1.0)
Version 1.0
No changes
SmartConnect Node (1.0)
Version 1.0 (Rev. 13)
Feature Enhancement: Support ID_WIDTH=0 to support (experimental) Enhanced low area mode automation to support cascaded SI and MI when all reachable slave endpoints are AXI4Lite 32-bit.
Feature Enhancement: Support FIFO_TYPE=3 to support (experimental) Reduced AXI4 Area mode when no width-conv and no clock-conv among all SC interfaces.
SmartConnect SC2AXI Bridge (1.0)
Version 1.0 (Rev. 7)
No changes
SmartConnect Switchboard (1.0)
Version 1.0 (Rev. 6)
No changes
SMPTE SD/HD/3G-SDI (3.0)
Version 3.0 (Rev. 9)
No changes
SMPTE UHD-SDI (1.0)
Version 1.0 (Rev. 8)
No changes
SMPTE UHD-SDI RX (1.0)
Version 1.0 (Rev. 1)
Removed set_max_delay constraints from XDC
Integrated XPM_CDC in cross_clk_reg.vhd and cross_clk_bus.vhd Modules
Added HFR support in IP for 12G and 6G SDI 10bit
SMPTE UHD-SDI RX SUBSYSTEM (2.0)
Version 2.0 (Rev. 8)
Bug Fix: Integrated XPM CDC module instead of double registering in AXI4-Lite Interface module
Bug Fix: Removed unsafe max_delay Timing constraints in core
Feature Enhancement: Added support for 1920x1080p120Hz (6G YUV4:2:2) at AXI4-Stream Level
Feature Enhancement: Added SDI Audio Video pass-through design for VCK190 Evaluation kit
Revision change in one or more subcores
SMPTE UHD-SDI TX (1.0)
Version 1.0 (Rev. 1)
Removed set_max_delay constraints from XDC
Integrated XPM_CDC in cross_clk_reg.vhd and cross_clk_bus.vhd Modules
Added HFR feature support in IP for 12G and 6G 10bit
SMPTE UHD-SDI TX SUBSYSTEM (2.0)
Version 2.0 (Rev. 8)
Bug Fix: Integrated XPM CDC module instead of double registering in AXI4-Lite Interface module
Bug Fix: Removed unsafe max_delay Timing constraints in core
Feature Enhancement: Added support for 1920x1080p120Hz (6G YUV4:2:2) at AXI4-Stream Level
Revision change in one or more subcores
Soft ECC Proxy (1.0)
Version 1.0 (Rev. 1)
No changes
Soft Error Mitigation (4.1)
Version 4.1 (Rev. 13)
No changes
Soft-Decision FEC (1.1)
Version 1.1 (Rev. 7)
Bug Fix: Correction to example design helper IP driver Makefiles to support Windows tool chain.
Other: Refreshed example design helper IP for latest tool compatibility and associated example design changes.
SPDIF/AES3 (2.0)
Version 2.0 (Rev. 24)
General: Bug Fixes
Stream Traffic Manager (1.0)
Version 1.0
No changes
Switch Core Top (1.0)
Version 1.0 (Rev. 9)
Revision change in one or more subcores
System Cache (5.0)
Version 5.0 (Rev. 5)
Bug Fix: Fixed CXS link status transitions
Bug Fix: Fixed CCIX message race condition for response and request
Bug Fix: Fixed CCIX and CHI cache line status for snoop conflicts
Feature Enhancement: Added CHI link down capability
Other: Always use XPM memory for Versal ACAP devices
System ILA (1.1)
Version 1.1 (Rev. 10)
Revision change in one or more subcores
System Management Wizard (1.3)
Version 1.3 (Rev. 14)
General: Increased Temperature range.
Time-Aware DMA (1.0)
Version 1.0 (Rev. 8)
Revision change in one or more subcores
Timer Sync 1588 (1.2)
Version 1.2 (Rev. 4)
No changes
TMR Comparator (1.0)
Version 1.0 (Rev. 4)
No changes
TMR Inject (1.0)
Version 1.0 (Rev. 4)
No changes
TMR Manager (1.0)
Version 1.0 (Rev. 7)
General: Ensure that example design generation works with core container enabled
TMR Soft Error Mitigation Interface (1.0)
Version 1.0 (Rev. 18)
Revision change in one or more subcores
TMR Voter (1.0)
Version 1.0 (Rev. 3)
No changes
Tri Mode Ethernet MAC (9.0)
Version 9.0 (Rev. 19)
Bug Fix: Support Added for Half Duplex Mode Simulation in example design
Revision change in one or more subcores
TSN Endpoint Block (1.0)
Version 1.0 (Rev. 9)
Revision change in one or more subcores
TSN Tri Mode Ethernet MAC (1.0)
Version 1.0 (Rev. 6)
Revision change in one or more subcores
UHD-SDI Audio (2.0)
Version 2.0 (Rev. 4)
General: Added auto device support based on GT Type
General: Non-Sequential Audio channels order in NTSC resolution is fixed for Sequential order
UHD-SDI GT (2.0)
Version 2.0 (Rev. 5)
Bug Fix: Fixed issue DRPCLK is not passed and is fixed as 100Mhz in case of multilink GT (AR76183)
New Feature: Added Tx_Only Data Flow option
Revision change in one or more subcores
UHD-SDI Video Pattern Generator (1.0)
Version 1.0 (Rev. 1)
No changes
UltraScale 100G Ethernet Subsystem (2.6)
Version 2.6 (Rev. 4)
Bug Fix: Added watch dog timer reset logic for RX datapath only instead of RX and TX
Revision change in one or more subcores
UltraScale FPGA Gen3 Integrated Block for PCI Express (4.4)
Version 4.4 (Rev. 11)
General: Added civ devices vu080 device
Revision change in one or more subcores
UltraScale FPGAs Transceivers Wizard (1.7)
Version 1.7 (Rev. 10)
General: Added support for additional devices
Revision change in one or more subcores
UltraScale Soft Error Mitigation (3.1)
Version 3.1 (Rev. 19)
General: Added support for additional UltraScale+ devices
UltraScale+ 100G Ethernet Subsystem (3.1)
Version 3.1 (Rev. 4)
Bug Fix: Added watchdog timer reset logic for RX datapath only instead of RX and TX
Bug Fix: Updated the missing connections on the tx_preamble and rx_preamble signals within the LBUS2AXIS and AXIS2LBUS module for GT in example design configuration
Bug Fix: Fixed the rx_preamble alignment issue with the 1st RX_TDATA and RX_TVALID for the AXIS mode configuration
Other: Added new UltraScale+ devices support
Revision change in one or more subcores
UltraScale+ Integrated Block (PCIE4) for PCI Express (1.3)
Version 1.3 (Rev. 13)
Bug Fix: updated MSIX table size in MSIX External mode
Revision change in one or more subcores
UltraScale+ Integrated Block (PCIE4C) for PCI Express (1.0)
Version 1.0 (Rev. 14)
General: Added xcux35, xcvu19p_CIV, xcvu31p_CIV and xcvu45p_CIV device support.
General: Fixed TIMING 38-3 warnings and updated multi cycle path constraints.
Revision change in one or more subcores
UltraScale+ PHY for PCI Express (1.0)
Version 1.0 (Rev. 17)
Revision change in one or more subcores
Universal Serial XGMII Ethernet Subsystem (1.2)
Version 1.2 (Rev. 2)
General: updated util_ds_buf_v2_1 to util_ds_buf_v2_2
General: Added for new device support
Revision change in one or more subcores
URAM Read Back (1.0)
Version 1.0 (Rev. 2)
Feature Enhancement: Parameter Configurable option added for Restore Command with default as enabled.
Feature Enhancement: Parameter Configurable option added to disable CDC logic with default as enable CDC.
Feature Enhancement: Parameter Configurable option added for Read Batch Command with default as enabled.
Feature Enhancement: Support added to receive command which initiates single read on both of the ports with different addresses.
Utility Reduced Logic (2.0)
Version 2.0 (Rev. 4)
No changes
Utility Vector Logic (2.0)
Version 2.0 (Rev. 1)
No changes
Versal ACAP 100G Multirate Ethernet MAC (MRMAC) (1.4)
Version 1.4
Feature Enhancement: Versal GTM support added for MRMAC.
Feature Enhancement: Block Automation updated.
Feature Enhancement: PTP 1588 updates in example design.
Feature Enhancement: Narrow mode GT Support added.
Feature Enhancement: Example design update and timing improvement.
Feature Enhancement: Example design supports direct targeting for VPK120.
Feature Enhancement: Port changes for GT interface.
Feature Enhancement: Preset name change and new presets added.
Revision change in one or more subcores
Versal ACAP 600G Channelized Multirate Ethernet MAC (DCMAC) (1.1)
Version 1.1
Feature Enhancement: Added DCMAC with GTM features support
Feature Enhancement: Added FEC-Only mode support
Feature Enhancement: Updated power attributes for DCMAC
Feature Enhancement: Added other GT ref clock frequencies support for GTYP and GTM
Other: GT Pin Loc provided for DCMAC with GTM example design to support the VPK120 board
Revision change in one or more subcores
Versal ACAP Integrated Block for PCI Express (1.0)
Version 1.0 (Rev. 7)
General: Updated Gen5 parameters for hardware link up
Revision change in one or more subcores
Versal ACAP PHY for PCI Express (1.0)
Version 1.0 (Rev. 6)
General: Updated Gen5 parameters for hardware link up
General: Updated Cursor values in module PHY IP TXEQ
Versal ACAP XDMA Subsystem for PCI Express (2.0)
Version 2.0 (Rev. 5)
Revision change in one or more subcores
Versal ACAPs Transceivers Bridge IP (1.1)
Version 1.1 (Rev. 4)
General: Added new transceiver configuration preset options for GTYP and GTM
Revision change in one or more subcores
Versal ACAPs Transceivers Reset IP (1.1)
Version 1.1 (Rev. 1)
General: Added support for additional devices with GTYP and GTM
Versal ACAPs Transceivers Wizard (1.1)
Version 1.1 (Rev. 4)
General: Added new transceiver configuration preset options for GTYP and GTM
Revision change in one or more subcores
Versal DDR4 Memory Controller (1.0)
Version 1.0 (Rev. 2)
No changes
Versal GT Controller for DP and SDI (1.0)
Version 1.0 (Rev. 3)
General: Resolved CDC error
General: Added configurable Options for picxo and pll selection
General: Added Datapath reset for DP
Revision change in one or more subcores
Versal QDRIV SRAM (1.0)
Version 1.0 (Rev. 4)
Port Change: Removed port qvlda, qvldb, dinva, and dinvb
Other: Updated for 2021.1
Revision change in one or more subcores
Versal Soft DDR4 Memory Controller (1.0)
Version 1.0 (Rev. 5)
General: updated for 2021.1
Revision change in one or more subcores
Versal Soft RLDRAM3 Memory Controller (1.0)
Version 1.0 (Rev. 6)
General: updated for 2021.1
Revision change in one or more subcores
Video AXI4S Remapper (1.1)
Version 1.1 (Rev. 2)
General: Revision change in one or more subcores.
Revision change in one or more subcores
Video Color Space Conversion and Correction (1.1)
Version 1.1 (Rev. 2)
Revision change in one or more subcores
Video Deinterlacer (5.1)
Version 2.2 (Rev. 2)
Revision change in one or more subcores
Video DisplayPort 1.4 RX Subsystem (3.0)
Version 3.0 (Rev. 3)
Bug Fix: Updated s_axis_phy_rx_sb_status_tdata width to remove Critical Warnings
New Feature: HDCP 2.3 repeater support
Feature Enhancement: Updates for CTS test 5.2.2.3. DPCD 0x205 register bit[1] is made 0 when Audio mute bit in VBID is set (in SST mode).
Feature Enhancement: Updates for CTS test 5.2.1.7. Fixed the issue of corrupted EDID read.
Feature Enhancement: Updates for CTS test 5.2.2.5. HDCP1.3/2.2 specific DPCD read/write interrupts are inhibited when corresponding parameters are not enabled in the system.
Feature Enhancement: Updates for CTS test 5.2.2.6. Added new AXI-4 Lite register bit [8] at 0x464 to control DPCD's 0x0004 bit [0]
Revision change in one or more subcores
Video DisplayPort 1.4 TX Subsystem (3.0)
Version 3.0 (Rev. 3)
Feature Enhancement: Added INCLUDE_DUAL_SPLITTER parameter to include/exclude 'Dual Splitter' module in MST with AXI-4 Stream interface configuration
Revision change in one or more subcores
Video Frame Buffer Read (2.2)
Version 2.2 (Rev. 2)
General: Added Versal example design support
Revision change in one or more subcores
Video Frame Buffer Write (2.2)
Version 2.2 (Rev. 2)
General: Added example design support for various IPs
Revision change in one or more subcores
Video Horizontal Chroma Resampler (1.1)
Version 1.1 (Rev. 2)
Revision change in one or more subcores
Video Horizontal Scaler (1.1)
Version 1.1 (Rev. 2)
Revision change in one or more subcores
Video In to AXI4-Stream (4.0)
Version 4.0 (Rev. 9)
No changes
Video Letterbox Engine (1.1)
Version 1.1 (Rev. 2)
Revision change in one or more subcores
Video Mixer (5.2)
Version 5.2
General: Removal of redundant registers
Revision change in one or more subcores
Video Multi-Scaler (1.2)
Version 1.2 (Rev. 1)
General: Added Versal example design support
Video PHY Controller (2.2)
Version 2.2 (Rev. 10)
General: DP Max rate restricted to 5.4 for -1 and -2LV
Revision change in one or more subcores
Video Processing Subsystem (2.3)
Version 2.3 (Rev. 2)
General: Added Versal example design support
Revision change in one or more subcores
Video Scene Change Detection (1.1)
Version 1.1 (Rev. 2)
General: v_scenechange_v1_1:CHANGELOG:Wrong version/revision
Video Test Pattern Generator (8.1)
Version 8.1 (Rev. 2)
General: CHANGELOG:Missing change descriptions
Revision change in one or more subcores
Video Timing Controller (6.2)
Version 6.2 (Rev. 2)
General: Support for framebuffer-less pass-through system in adaptive sync mode
Video to SDI TX Bridge (2.0)
Version 2.0
No changes
Video Vertical Chroma Resampler (1.1)
Version 1.1 (Rev. 2)
Revision change in one or more subcores
Video Vertical Scaler (1.1)
Version 1.1 (Rev. 2)
Revision change in one or more subcores
video_cke_sync (1.0)
Version 1.0
No changes
VIO (Virtual Input/Output with AXIS Interface) (1.0)
Version 1.0 (Rev. 4)
General: Added DRC on total number of bits selection
VIO (Virtual Input/Output) (3.0)
Version 3.0 (Rev. 20)
General: Updated the MMCM configuration for example design
Virtex UltraScale+ FPGAs GTM Transceivers Wizard (1.0)
Version 1.0 (Rev. 11)
Revision change in one or more subcores
Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.3)
Version 4.3 (Rev. 9)
No changes
Viterbi Decoder (9.1)
Version 9.1 (Rev. 12)
No changes
Vitis Networking P4 (1.0)
Version 1.0
General: First release to Vivado
XADC Wizard (3.3)
Version 3.3 (Rev. 8)
No changes
XHMC (1.0)
Version 1.0 (Rev. 13)
Revision change in one or more subcores
XRAM (Accelerated RAM) (1.0)
Version 1.0
No changes
Zynq UltraScale+ MPSoC (3.3)
Version 3.3 (Rev. 5)
Revision change in one or more subcores
Zynq UltraScale+ RF Data Converter (2.5)
Version 2.5
Bug Fix: Moved the setting of the converter interrupt registers to later in the start-up sequence to ensure correct operation
Bug Fix: Fixed tdd_mode real time signal connections in dual channel DACs
Bug Fix: Fixed ADC configuration for channels with dither disabled in gen 3 device
Bug Fix: Fixed SYSREF passing to ADCs when the SYSREF source DAC is disabled in gen 3 devices
Bug Fix: Fixed rounding error in fabric clock frequency setting
Bug Fix: Fixed issue with the opening of RF Analyzer example designs when multi tile sync is enabled in some tiles but not others
New Feature: Added DAC link coupling option for gen 3 devices
New Feature: Set TDD registers to power down without driver involvement in gen 3 devices
New Feature: Added observation channel configuration for gen 3 devices
New Feature: Added real time signal for datapath overflow
Other: Updated clock distribution options in gen 3 devices
Other: Updated PLL reference clock frequency range
Other: Changed ADC input in demo testbench to have a full scale range of 1V in gen 3 devices
Other: Updated range of PLL reference clock warning to match the datasheet values
Other: Added default address range of 256k
Other: Removed analog clock detection option from GUI
Other: Updated the example design Questa elaboration options to allow for simulation with Questa 2020.4
ZYNQ UltraScale+ SYNC IP (1.0)
Version 1.0 (Rev. 6)
Revision change in one or more subcores
ZYNQ UltraScale+ VCU (1.2)
Version 1.2 (Rev. 5)
Port Change: None
Bug Fix: fixed the GUI bug for number of streams
Feature Enhancement: None
Other: None
ZYNQ UltraScale+ VCU DDR4 Controller (1.1)
Version 1.1 (Rev. 5)
Port Change: None
Bug Fix: None
Feature Enhancement: Added custom memory addition support
Other: None
Revision change in one or more subcores
ZYNQ7 Processing System (5.5)
Version 5.5 (Rev. 6)
No changes
ZYNQ7 Processing System VIP (1.0)
Version 1.0 (Rev. 12)
Revision change in one or more subcores
ZYNQMPSOC Processing System VIP (1.0)
Version 1.0 (Rev. 10)
Revision change in one or more subcores
| AR# 76541 | |
|---|---|
| 日期 | 06/28/2021 |
| 状态 | Active |
| Type | 版本说明 |
| Tools | |