This Answer Record contains a comprehensive list of IP change log information from Vivado 2017.2 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.
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10G Ethernet MAC (15.1)
* Version 15.1 (Rev. 3)
* General: Updated to support production silicon for these Spartan-7 parts - 7s50csga324 and 7s50fgga484
10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)
* Version 6.0 (Rev. 9)
* Bug Fix: Removing driving rxrecclk_out via BUFH
* Bug Fix: Fix for cable pull logic
* Other: Enabling FB packages for Kintex-7 devices
* Other: Changed version of helper core gtwizard_UltraScale from v1_6 to v1_7
10G Ethernet Subsystem (3.1)
* Version 3.1 (Rev. 5)
* Bug Fix: Added BUFH on rxrecclk_out being fed to timer_sync_rx module
* Revision change in one or more subcores
10G/25G Ethernet Subsystem (2.2)
* Version 2.2
* Feature Enhancement: Added 25G support for Kintex UltraScale+ and Zynq UltraScale+ -1 and -1L speed grades
* Feature Enhancement: Updated for CR
* Revision change in one or more subcores
1G/2.5G Ethernet PCS/PMA or SGMII (16.1)
* Version 16.1
* gtpowergood output port added for UltraScale and UltraScale+ devices in modes with transceivers.
* UltraScale+ production support added.
32-bit Initiator/Target for PCI (7-Series) (5.0)
* Version 5.0 (Rev. 8)
* No changes
3GPP LTE Channel Estimator (2.0)
* Version 2.0 (Rev. 13)
* No changes
3GPP LTE MIMO Decoder (3.0)
* Version 3.0 (Rev. 12)
* No changes
3GPP LTE MIMO Encoder (4.0)
* Version 4.0 (Rev. 11)
* No changes
3GPP Mixed Mode Turbo Decoder (2.0)
* Version 2.0 (Rev. 13)
* No changes
3GPP Turbo Encoder (5.0)
* Version 5.0 (Rev. 11)
* No changes
3GPPLTE Turbo Encoder (4.0)
* Version 4.0 (Rev. 12)
* No changes
40G/50G Ethernet Subsystem (2.2)
* Version 2.2
* Feature Enhancement: CR
* Feature Enhancement: Updated GTWIZ version from 1.6 to 1.7
* Revision change in one or more subcores
64-bit Initiator/Target for PCI (7-Series) (5.0)
* Version 5.0 (Rev. 8)
* No changes
7 Series FPGAs Transceivers Wizard (3.6)
* Version 3.6 (Rev. 7)
* Bug Fix: txpmareset port is added as optional port
7 Series Integrated Block for PCI Express (3.3)
* Version 3.3 (Rev. 4)
* No changes
AHB-Lite to AXI Bridge (3.0)
* Version 3.0 (Rev. 11)
* Revision change in one or more subcores
AXI 1G/2.5G Ethernet Subsystem (7.1)
* Version 7.1
* General: Refer to tri_mode_ethernet_mac v9.0 and gig_ethernet_pcs_pma v16_1 core change logs for changes in the sub cores of this core.
* General: Added output port gt_powergood in case of UltraScale and UltraScale+ devices in modes using transceivers
* Revision change in one or more subcores
AXI AHBLite Bridge (3.0)
* Version 3.0 (Rev. 11)
* Revision change in one or more subcores
AXI AMM Bridge (1.0)
* Version 1.0 (Rev. 3)
* General: Default values of BASE and HIGH address updated in RTL to match with GUI
* Revision change in one or more subcores
AXI APB Bridge (3.0)
* Version 3.0 (Rev. 11)
* Revision change in one or more subcores
AXI BRAM Controller (4.0)
* Version 4.0 (Rev. 11)
* No changes
AXI Bridge for PCI Express Gen3 Subsystem (3.0)
* Version 3.0 (Rev. 3)
* Bug Fix: PCI Express Extended Configuration Space Enable parameter enables config extended interface.
* Bug Fix: Optional ports rq_tuser and cq_tuser widths are corrected when ATS/PRI is enabled.
* Bug Fix: Bridge Info UpConfig capable bit is obsolete.
* Bug Fix: Enabled selection of PLL type when Gen2 link speed is selected.
* Bug Fix: Disable Slave AXI Bridge Timeout Counter and use PCIe Hard Block Timeout Counter for Vrtex7-XT and UltraScale devices.
* Feature Enhancement: Allow one beat narrow burst transfer to be passed with no modification or packing to support IO-only capable devices.
* Revision change in one or more subcores
AXI CAN (5.0)
* Version 5.0 (Rev. 16)
* Revision change in one or more subcores
AXI Central Direct Memory Access (4.1)
* Version 4.1 (Rev. 13)
* Revision change in one or more subcores
AXI Chip2Chip Bridge (4.3)
* Version 4.3 (Rev. 1)
* Bug Fix: Reset sequence update for better timing in SelectIO mode.
* Revision change in one or more subcores
AXI Clock Converter (2.1)
* Version 2.1 (Rev. 12)
* Revision change in one or more subcores
AXI Crossbar (2.1)
* Version 2.1 (Rev. 14)
* Revision change in one or more subcores
AXI Data FIFO (2.1)
* Version 2.1 (Rev. 12)
* Revision change in one or more subcores
AXI Data Width Converter (2.1)
* Version 2.1 (Rev. 13)
* Revision change in one or more subcores
AXI DataMover (5.1)
* Version 5.1 (Rev. 15)
* General: Source HDL files updated for internal debugging. No Functional changes
* Revision change in one or more subcores
AXI Direct Memory Access (7.1)
* Version 7.1 (Rev. 14)
* Revision change in one or more subcores
AXI EMC (3.0)
* Version 3.0 (Rev. 13)
* General: Updated to correct IP Integrator automation for EMC_INTF interface. No Functional changes
* Revision change in one or more subcores
AXI EPC (2.0)
* Version 2.0 (Rev. 16)
* Revision change in one or more subcores
AXI Ethernet Buffer (2.0)
* Version 2.0 (Rev. 15)
* No changes
AXI Ethernet Clocking (2.0)
* Version 2.0 (Rev. 2)
* No changes
AXI EthernetLite (3.0)
* Version 3.0 (Rev. 11)
* Revision change in one or more subcores
AXI GPIO (2.0)
* Version 2.0 (Rev. 15)
* Revision change in one or more subcores
AXI HWICAP (3.0)
* Version 3.0 (Rev. 17)
* General: Updated the comments in XDC files. No Functional changes
* Revision change in one or more subcores
AXI IIC (2.0)
* Version 2.0 (Rev. 16)
* Revision change in one or more subcores
AXI Interconnect (2.1)
* Version 2.1 (Rev. 14)
* Revision change in one or more subcores
AXI Interrupt Controller (4.1)
* Version 4.1 (Rev. 10)
* Feature Enhancement: Issue warning for improper connection of the interrupt bus interface
AXI Lite IPIF (3.0)
* Version 3.0 (Rev. 4)
* No changes
AXI MMU (2.1)
* Version 2.1 (Rev. 11)
* Revision change in one or more subcores
AXI Master Burst (2.0)
* Version 2.0 (Rev. 7)
* No changes
AXI Memory Mapped To PCI Express (2.8)
* Version 2.8 (Rev. 5)
* Bug Fix: Added Root Port Interrupt FIFO Depth GUI selection.
* Revision change in one or more subcores
AXI Memory Mapped to Stream Mapper (1.1)
* Version 1.1 (Rev. 12)
* Revision change in one or more subcores
AXI Performance Monitor (5.0)
* Version 5.0 (Rev. 15)
* Revision change in one or more subcores
AXI Protocol Checker (1.1)
* Version 1.1 (Rev. 14)
* General: Minor timing optimization for synthesis
* General: X-propration checks on pc interface for simulation
* General: Improved IP Integrator automation of MAX_RD_BURSTS and MAX_WR_BURSTS
* Revision change in one or more subcores
AXI Protocol Converter (2.1)
* Version 2.1 (Rev. 13)
* Revision change in one or more subcores
AXI Quad SPI (3.2)
* Version 3.2 (Rev. 12)
* General: RTL updated to take care of incorrect IOB property
* Revision change in one or more subcores
AXI Register Slice (2.1)
* Version 2.1 (Rev. 13)
* Revision change in one or more subcores
AXI SmartConnect (1.0)
* Version 1.0 (Rev. 5)
* Resolved various bugs.
* Revision change in one or more subcores
AXI TFT Controller (2.0)
* Version 2.0 (Rev. 17)
* Revision change in one or more subcores
AXI Timebase Watchdog Timer (3.0)
* Version 3.0 (Rev. 5)
* Revision change in one or more subcores
AXI Timer (2.0)
* Version 2.0 (Rev. 15)
* Revision change in one or more subcores
AXI Traffic Generator (2.0)
* Version 2.0 (Rev. 14)
* General: GUI updated to prevent incorrect IP configuration
* Revision change in one or more subcores
AXI UART16550 (2.0)
* Version 2.0 (Rev. 15)
* Revision change in one or more subcores
AXI USB2 Device (5.0)
* Version 5.0 (Rev. 14)
* Revision change in one or more subcores
AXI UART Lite (2.0)
* Version 2.0 (Rev. 17)
* Revision change in one or more subcores
AXI Verification IP (1.0)
* Version 1.0 (Rev. 2)
* Sub core IP clk_wiz version changed to 5.4
* Added new features -halt_master
* Clean up codes
* Fixed bd.tcl for IP Integrator propagation
* Revision change in one or more subcores
AXI Video Direct Memory Access (6.3)
* Version 6.3 (Rev. 1)
* General: XDC update. No functional changes
* Revision change in one or more subcores
AXI Virtual FIFO Controller (2.0)
* Version 2.0 (Rev. 15)
* Revision change in one or more subcores
AXI-Stream FIFO (4.1)
* Version 4.1 (Rev. 10)
* Revision change in one or more subcores
AXI4-Stream Accelerator Adapter (2.1)
* Version 2.1 (Rev. 11)
* No changes
AXI4-Stream Broadcaster (1.1)
* Version 1.1 (Rev. 13)
* Revision change in one or more subcores
AXI4-Stream Clock Converter (1.1)
* Version 1.1 (Rev. 14)
* Revision change in one or more subcores
AXI4-Stream Combiner (1.1)
* Version 1.1 (Rev. 12)
* Revision change in one or more subcores
AXI4-Stream Data FIFO (1.1)
* Version 1.1 (Rev. 14)
* Revision change in one or more subcores
AXI4-Stream Data Width Converter (1.1)
* Version 1.1 (Rev. 12)
* Revision change in one or more subcores
AXI4-Stream Interconnect (2.1)
* Version 2.1 (Rev. 14)
* Revision change in one or more subcores
AXI4-Stream Protocol Checker (1.1)
* Version 1.1 (Rev. 13)
* Revision change in one or more subcores
AXI4-Stream Register Slice (1.1)
* Version 1.1 (Rev. 13)
* Revision change in one or more subcores
AXI4-Stream Subset Converter (1.1)
* Version 1.1 (Rev. 13)
* Revision change in one or more subcores
AXI4-Stream Switch (1.1)
* Version 1.1 (Rev. 13)
* Revision change in one or more subcores
AXI4-Stream Verification IP (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
AXI4-Stream to Video Out (4.0)
* Version 4.0 (Rev. 6)
* No changes
Accumulator (12.0)
* Version 12.0 (Rev. 10)
* No changes
Adder/Subtracter (12.0)
* Version 12.0 (Rev. 10)
* No changes
Aurora 64B66B (11.2)
* Version 11.2 (Rev. 1)
* Bug Fix: for multi-quad GTY based designs with line rate more than 16.375 gbps the reference clock locations are added in XDC
* Other: UltraScale GT Wizard version upgrade.
Aurora 8B10B (11.1)
* Version 11.1 (Rev. 1)
* Bug Fix: Unused gtrxresetseq DRP signals removed from TX-simplex based designs
* Other: UltraScale GT Wizard version upgrade.
Binary Counter (12.0)
* Version 12.0 (Rev. 10)
* No changes
Block Memory Generator (8.3)
* Version 8.3 (Rev. 6)
* No changes
CANFD (1.0)
* Version 1.0 (Rev. 6)
* Revision change in one or more subcores
CIC Compiler (4.0)
* Version 4.0 (Rev. 11)
* No changes
CORDIC (6.0)
* Version 6.0 (Rev. 11)
* No changes
CPRI (8.7)
* Version 8.7 (Rev. 3)
* Bug Fix: Fixed bug where remote alarms were not being set correctly.
* Bug Fix: Fixed bug where FEC line rates were not using 64b/66b scrambling as per the CPRI specification.
* Bug Fix: Fixed incorrect line rate and clock frequencies on UltraScale GTHE3 cores using 12.1G line rate support and 307.2/245.76MHZ ref clock.
* Other: Updated to use version 1.7 of the UltraScale GT Wizard.
* Revision change in one or more subcores
Chroma Resampler (4.0)
* Version 4.0 (Rev. 11)
* No changes
Clocking Wizard (5.4)
* Version 5.4 (Rev. 1)
* General: Internal GUI changes. No effect on the customer design.
Color Correction Matrix (6.0)
* Version 6.0 (Rev. 12)
* No changes
Color Filter Array Interpolation (7.0)
* Version 7.0 (Rev. 11)
* No changes
Complex Multiplier (6.0)
* Version 6.0 (Rev. 12)
* No changes
Concat (2.1)
* Version 2.1 (Rev. 1)
* No changes
Constant (1.1)
* Version 1.1 (Rev. 3)
* No changes
Convolution Encoder (9.0)
* Version 9.0 (Rev. 11)
* No changes
DDR3 SDRAM (MIG) (1.4)
* Version 1.4 (Rev. 1)
* Bug Fix: example_tb_phy update
* Feature Enhancement: Added GUI option for Partial Reconfiguration flow support as Disable OBUF on reset
* Feature Enhancement: Addition of wr_rd_complete port in example_top file for PHY only and ping-pong PHY.
* Revision change in one or more subcores
DDR4 SDRAM (MIG) (2.2)
* Version 2.2 (Rev. 1)
* Bug Fix: tMRD value updated to 8 for 075E speed grade memory devices.
* Bug Fix: Calibration SW code fixes.
* Feature Enhancement: Added Self-refresh/Save-restore support for 3DS parts.
* Feature Enhancement: Updated 3DS part names to add package info and 3DS part upgrade flow changes for package addition in 3DS parts names.
* Feature Enhancement: Added GUI option for Partial Reconfiguration flow support as Disable OBUF on reset_n.
* Feature Enhancement: GUI update to provide detailed information about memory part in memory details.
* Feature Enhancement: Addition of wr_rd_complete port in example_top file for PHY only and ping-pong PHY.
* Revision change in one or more subcores
DDS Compiler (6.0)
* Version 6.0 (Rev. 13)
* No changes
DMA/Bridge Subsystem for PCI Express (PCIe) (3.1)
* Version 3.1 (Rev. 1)
* Bug Fix: PCI Express Extended Configuration Space Enable parameter enables config extended interface
* Bug Fix: Limit PCIe BAR and address translation value for AXI Lite Master interface to 32-bit only
* Bug Fix: Limit PCIe BAR and address translation value for DMA Bridge mode up to the chosen AXI Address Width only
* Bug Fix: Disable Slave AXI Bridge Timeout Counter and use PCIe Hard Block Timeout Counter for Virtex-7 XT, UltraScale and UltraScale+ devices
* Bug Fix: Handle Message TLP for 7 Series Gen2 DMA
* Feature Enhancement: Added support for xczu27dr device
* Revision change in one or more subcores
DSP48 Macro (3.0)
* Version 3.0 (Rev. 14)
* No changes
DUC/DDC Compiler (3.0)
* Version 3.0 (Rev. 11)
* No changes
Debug Bridge (2.0)
* Version 2.0 (Rev. 1)
* Added new device support for XA Zynq UltraScale+ MPSoC devices
Discrete Fourier Transform (4.0)
* Version 4.0 (Rev. 13)
* No changes
DisplayPort (7.0)
* Version 7.0 (Rev. 5)
* General: Marked devices as Discontinued
* Revision change in one or more subcores
DisplayPort RX Subsystem (2.0)
* Version 2.0 (Rev. 5)
* Revision change in one or more subcores
DisplayPort TX Subsystem (2.0)
* Version 2.0 (Rev. 5)
* Feature Enhancement: Updated holding buffer to Dist RAM
* Revision change in one or more subcores
Distributed Memory Generator (8.0)
* Version 8.0 (Rev. 11)
* No changes
Divider Generator (5.1)
* Version 5.1 (Rev. 11)
* No changes
Double Data Rate Sampling (1.0)
* Version 1.0
* No changes
ECC (2.0)
* Version 2.0 (Rev. 12)
* No changes
Ethernet PHY MII to Reduced MII (2.0)
* Version 2.0 (Rev. 15)
* Revision change in one or more subcores
FIFO Generator (13.1)
* Version 13.1 (Rev. 4)
* No changes
FIR Compiler (7.2)
* Version 7.2 (Rev. 8)
* No changes
Fast Fourier Transform (9.0)
* Version 9.0 (Rev. 12)
* No changes
Fiber Channel 32GFC RS-FEC (1.0)
* Version 1.0 (Rev. 3)
* General: Migrated example design to latest GT Wizard IP.
* General: Modified example design for improved VHDL simulation support.
* Revision change in one or more subcores
Fixed Interval Timer (2.0)
* Version 2.0 (Rev. 8)
* No changes
FlexO 100G RS-FEC (1.0)
* Version 1.0 (Rev. 3)
* Revision change in one or more subcores
Floating-point (7.1)
* Version 7.1 (Rev. 4)
* No changes
G.709 FEC Encoder/Decoder (2.3)
* Version 2.3
* No changes
G.975.1 EFEC I.4 Encoder/Decoder (1.0)
* Version 1.0 (Rev. 13)
* No changes
G.975.1 EFEC I.7 Encoder/Decoder (2.0)
* Version 2.0 (Rev. 14)
* No changes
Gamma Correction (7.0)
* Version 7.0 (Rev. 12)
* No changes
Gmii to Rgmii (4.0)
* Version 4.0 (Rev. 4)
* No changes
HDCP (1.0)
* Version 1.0 (Rev. 2)
* No changes
HDCP 2.2 Cipher (1.0)
* Version 1.0 (Rev. 1)
* No changes
HDCP 2.2 Montgomery Modular Multiplier (1.0)
* Version 1.0 (Rev. 2)
* General: Optimized for resource reduction of LUT and FF
HDCP 2.2 Random Number Generator (1.0)
* Version 1.0 (Rev. 1)
* No changes
HDCP 2.2 Receiver (1.0)
* Version 1.0 (Rev. 2)
* No changes
HDCP 2.2 Transmitter (1.0)
* Version 1.0 (Rev. 2)
* No changes
HDMI 1.4/2.0 Receiver (2.0)
* Version 1.1
* No changes
HDMI 1.4/2.0 Receiver Subsystem (2.0)
* Version 2.0 (Rev. 5)
* Bug Fix: Fixed Timing violation in Example design for Zynq devices
* Bug Fix: Fix to detect OESS encryption disablement when connected to a DVI source
HDMI 1.4/2.0 Transmitter (2.0)
* Version 1.1
* No changes
HDMI 1.4/2.0 Transmitter Subsystem (2.0)
* Version 2.0 (Rev. 5)
* Bug Fix: Fixed Timing violation in Example design for Zynq devices
High Speed SelectIO Wizard (3.2)
* Version 3.2 (Rev. 1)
* Bug Fix: Removed -name option in XDC constraints
IBERT 7 Series GTH (3.0)
* Version 3.0 (Rev. 16)
* No changes
IBERT 7 Series GTP (3.0)
* Version 3.0 (Rev. 15)
* No changes
IBERT 7 Series GTX (3.0)
* Version 3.0 (Rev. 16)
* No changes
IBERT 7 Series GTZ (3.1)
* Version 3.1 (Rev. 12)
* No changes
IBERT UltraScale GTH (1.3)
* Version 1.3 (Rev. 7)
* Updated to use latest subcore gtwizard_UltraScale_v1_7.
IBERT UltraScale GTY (1.2)
* Version 1.2 (Rev. 7)
* Updated to use latest subcore gtwizard_UltraScale_v1_7.
IEEE 802.3 25G RS-FEC (1.0)
* Version 1.0 (Rev. 5)
* General: Migrated example design to latest GT Wizard IP.
* Revision change in one or more subcores
IEEE 802.3 50G RS-FEC (1.0)
* Version 1.0 (Rev. 5)
* General: Migrated example design to latest GT Wizard IP.
* Revision change in one or more subcores
IEEE 802.3bj 100G RS-FEC (1.0)
* Version 1.0 (Rev. 9)
* General: Migrated example design to latest GT Wizard IP.
* Revision change in one or more subcores
ILA (Integrated Logic Analyzer) (6.2)
* Version 6.2 (Rev. 3)
* Added new XA Zynq UltraScale+ MPSoC device support
IOModule (3.1)
* Version 3.1 (Rev. 1)
* General: Set unused UART bits in voting signal to zero
Image Enhancement (8.0)
* Version 8.0 (Rev. 12)
* No changes
In System IBERT (1.0)
* Version 1.0 (Rev. 3)
* Updated to use latest subcore gtwizard_UltraScale_v1_7.
Interlaken 150G (2.2)
* Version 2.2
* Feature Enhancement: GTWIZ LOCATE USERE DATA WIDTH changed to Example design when GT in example design
* Feature Enhancement: CR
* Feature Enhancement: Updated GTWIZ version from 1.6 to 1.7
Interleaver/De-interleaver (8.0)
* Version 8.0 (Rev. 10)
* No changes
JESD204 (7.1)
* Version 7.1 (Rev. 3)
* General: Updated to use JESD204_PHY v3.4 with UltraScale GT wizard 1.7
* General: Modified example design to used gt_powergood signal from JESD204_PHY
JESD204 PHY (3.4)
* Version 3.4
* Feature Enhancement: Updated GT wizard to version 1.7
* Feature Enhancement: Added port gt_powergood for UltraScale and UltraScale+ devices
* Feature Enhancement: Added registers to enable programming the CPLL clock period calibration values for GTHE4 and GTYE4 when dynamically changing line rate
* Revision change in one or more subcores
JESD204C (1.0)
* Version 1.0 (Rev. 1)
* General: Updated to use JESD204_PHY v3.4 with UltraScale GT wizard 1.7
* General: Modified example design to used gt_powergood signal from JESD204_PHY
JTAG to AXI Master (1.2)
* Version 1.2 (Rev. 3)
* Added FIFO Generator constraints
LMB BRAM Controller (4.0)
* Version 4.0 (Rev. 12)
* Feature Enhancement: Support ECC with extended LMB address
LPDDR3 SDRAM (MIG) (1.0)
* Version 1.0 (Rev. 1)
* Feature Enhancement: SW/IP update to support of LPDDR3 IP with HR banks.
* Feature Enhancement: Addition of VIO and ILA while enabling ATG.
* Feature Enhancement: Rank, CS Width and Memory Component Width columns not required in custom part csv file.
* Revision change in one or more subcores
LTE DL Channel Encoder (3.0)
* Version 3.0 (Rev. 12)
* No changes
LTE Fast Fourier Transform (2.0)
* Version 2.0 (Rev. 13)
* No changes
LTE PUCCH Receiver (2.0)
* Version 2.0 (Rev. 11)
* No changes
LTE RACH Detector (3.0)
* Version 3.0
* No changes
LTE UL Channel Decoder (4.0)
* Version 4.0 (Rev. 12)
* No changes
Local Memory Bus (LMB) 1.0 (3.0)
* Version 3.0 (Rev. 9)
* No changes
MIPI CSI-2 RX Controller (1.0)
* Version 1.0 (Rev. 6)
* No changes
MIPI CSI-2 RX Subsystem (2.2)
* Version 2.2 (Rev. 1)
* Bug Fix: Corrected License status from Included to Purchase in the IP Catalog GUI
* Revision change in one or more subcores
MIPI CSI-2 TX Controller (1.0)
* Version 1.0 (Rev. 2)
* No changes
MIPI CSI-2 TX Subsystem (1.0)
* Version 1.0 (Rev. 3)
* Bug Fix: Corrected License status from Included to Purchase in the IP Catalog GUI
* Feature Enhancement: Support for non-continuous clock mode
* Revision change in one or more subcores
MIPI D-PHY (3.1)
* Version 3.1 (Rev. 1)
* Port Change: Added cl_txclkactivehs output port for D-PHY TX IP configuration
* Port Change: Added init_done output port to indicate D-PHY IP initialization completion
* Bug Fix: Fixed lane initialization status not getting reset when DPHY_EN bit of CONTROL register is deasserted
* Bug Fix: Added IOSTD constraints in example design for UltraScale+ device IP configuration
* Bug Fix: Added cl_txclkactivehs output port to indicate HS clock output timing after cl_txrequesths assertion
* Bug Fix: Added init_done output port to indicate D-PHY IP initialization completion
* Bug Fix: Fixed T pin of OBUFTDS toggling during Low-Power period in 7 Series D-PHY TX IP configuration
* Bug Fix: Fixed hs_rx_timeout inadvertently triggering issue for 3-lane D-PHY RX IP configuration
* Bug Fix: Fixed tangling system_rst_out output port in 7 Series D-PHY TX IP configuration
* Revision change in one or more subcores
MIPI DSI TX Controller (1.0)
* Version 1.0 (Rev. 4)
* No changes
MIPI DSI TX Subsystem (1.1)
* Version 1.1 (Rev. 3)
* Bug Fix: Corrected License status from Included to Purchase in the IP Catalog GUI
* Revision change in one or more subcores
Mailbox (2.1)
* Version 2.1 (Rev. 7)
* No changes
Memory Helper Core (1.4)
* Version 1.4
* No changes
Memory Interface Generator (MIG 7 Series) (4.0)
* Version 4.0 (Rev. 4)
* General: Vivado 2017.2 software support.
MicroBlaze (10.0)
* Version 10.0 (Rev. 3)
* General: Improve cache warning messages to avoid duplication
* General: Provide parameter to select asynchronous reset for debug external trace
MicroBlaze Debug Module (MDM) (3.2)
* Version 3.2 (Rev. 10)
* General: Provide parameter to select asynchronous reset for AXI Stream external trace
MicroBlaze MCS (3.0)
* Version 3.0 (Rev. 5)
* Revision change in one or more subcores
Multiplier (12.0)
* Version 12.0 (Rev. 12)
* No changes
Multiply Adder (3.0)
* Version 3.0 (Rev. 10)
* No changes
Mutex (2.1)
* Version 2.1 (Rev. 8)
* No changes
PCIe PHY IP (1.0)
* Version 1.0 (Rev. 5)
* Feature Enhancement: GTWizard Sub IP version update from v1_6 to v1_7
* Feature Enhancement: New output port "gt_gtpowergood" added for UltraScale+ devices
Partial Reconfiguration Controller (1.1)
* Version 1.1 (Rev. 3)
* General: No visible changes
Partial Reconfiguration Decoupler (1.0)
* Version 1.0 (Rev. 4)
* No changes
Peak Cancellation Crest Factor Reduction (6.1)
* Version 6.1 (Rev. 1)
* No changes
Processor System Reset (5.0)
* Version 5.0 (Rev. 11)
* No changes
QDRII+ SRAM (MIG) (1.4)
* Version 1.4 (Rev. 1)
* Bug Fix: Fixed bugs for 2017.2
* Revision change in one or more subcores
QDRIV SRAM (MIG) (2.0)
* Version 2.0 (Rev. 1)
* Bug Fix: Fixed bugs for 2017.2
* Revision change in one or more subcores
QDRIV SRAM PHY IP (2.0)
* Version 1.2
* No changes
QSGMII (3.4)
* Version 3.4
* Port Change: Added new output port gtpowergood_out
* Other: Changed version of helper core gig_ethernet_pcs_pma from v16_0 to v16_1
* Other: Changed version of helper core gtwizard_UltraScale from v1_6 to v1_7
RAM-based Shift Register (12.0)
* Version 12.0 (Rev. 10)
* No changes
RGB to YCrCb Color-Space Converter (7.1)
* Version 7.1 (Rev. 10)
* No changes
RLDRAM3 (MIG) (1.4)
* Version 1.4 (Rev. 1)
* Bug Fix: Fixed bugs for 2017.2
* Revision change in one or more subcores
RXAUI (4.4)
* Version 4.4
* Port Change: Added new output port gtpowergood_out
* Other: Changed version of helper core gtwizard_UltraScale from v1_6 to v1_7
* Other: Changed version of helper core XAUI from v12_2 to v12_3
Reed-Solomon Decoder (9.0)
* Version 9.0 (Rev. 12)
* No changes
Reed-Solomon Encoder (9.0)
* Version 9.0 (Rev. 11)
* No changes
S/PDIF (2.0)
* Version 2.0 (Rev. 16)
* Revision change in one or more subcores
SC EXIT (1.0)
* Version 1.0 (Rev. 4)
* No changes
SC MMU (1.0)
* Version 1.0 (Rev. 4)
* No changes
SC SI_CONVERTER (1.0)
* Version 1.0 (Rev. 4)
* No changes
SC SPLITTER (1.0)
* Version 1.0 (Rev. 2)
* No changes
SC TRANSACTION_REGULATOR (1.0)
* Version 1.0 (Rev. 5)
* General: Minor timing optimization
SMPTE SD/HD/3G-SDI (3.0)
* Version 3.0 (Rev. 8)
* No changes
SMPTE UHD-SDI (1.0)
* Version 1.0 (Rev. 4)
* No changes
SPI-4.2 (13.0)
* Version 13.0 (Rev. 10)
* No changes
SelectIO Interface Wizard (5.1)
* Version 5.1 (Rev. 9)
* No changes
Serial RapidIO Gen2 (4.1)
* Version 4.1
* General: UltraScale GT Wizard version update
SmartConnect AXI2SC Bridge (1.0)
* Version 1.0 (Rev. 5)
* Bug Fix: Resolve simulator compatibility issue
SmartConnect Node (1.0)
* Version 1.0 (Rev. 5)
* Bug Fix: Resolve simulator compatibility issue
SmartConnect SC2AXI Bridge (1.0)
* Version 1.0 (Rev. 5)
* Bug Fix: Resolve simulator compatibility issue
SmartConnect Switchboard (1.0)
* Version 1.0 (Rev. 4)
* No changes
Soft Error Mitigation (4.1)
* Version 4.1 (Rev. 9)
* Update SEM support label to Production for xc7z007s, xc7z012s, and xc7z014s. The IP is production for these devices as of 2017.1
System Cache (4.0)
* Version 4.0 (Rev. 2)
* No changes
System ILA (1.0)
* Version 1.0 (Rev. 3)
* XA Zynq UltraScale+ MPSoC support added
* Revision change in one or more subcores
System Management Wizard (1.3)
* Version 1.3 (Rev. 5)
* General: Internal GUI Updates. No effect on the customer design.
* General: Added support for ADC and DAC tile voltage monitoring.
TMR Comparator (1.0)
* Version 1.0
* No changes
TMR Inject (1.0)
* Version 1.0
* No changes
TMR Manager (1.0)
* Version 1.0
* No changes
TMR Soft Error Mitigation Interface (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
TMR Voter (1.0)
* Version 1.0
* No changes
Timer Sync 1588 (1.2)
* Version 1.2 (Rev. 4)
* No changes
Tri Mode Ethernet MAC (9.0)
* Version 9.0 (Rev. 8)
* General: Updated to support production silicon for these Spartan-7 parts - 7s50csga324 and 7s50fgga484
* General: Updated to support production silicon for UltraScale Plus family devices
* General: Virtex UltraScale Plus HBM device pre-production support
UltraScale 100G Ethernet Subsystem (2.2)
* Version 2.2
* Port Change: Added gt_powergood signal access to user
* Port Change: Added ctl_an_fec_25g_rs_request signal when ANLT enabled
* Feature Enhancement: Added RSFEC support for runtime switchable mode
* Revision change in one or more subcores
UltraScale FPGA Gen3 Integrated Block for PCI Express (4.3)
* Version 4.3 (Rev. 1)
* Bug Fix: PCI Express Extended Configuration Space Enable parameter enables config extended interface
* Revision change in one or more subcores
UltraScale FPGAs Transceivers Wizard (1.7)
* Version 1.7
* Feature Enhancement: gtpowergood_out is now enabled as default output port
* Feature Enhancement: Updated CPLL calibration block for TX and RX use cases for UltraScale+ devices
* Feature Enhancement: Adjusted line rate and associated frequency limits for -2LV speed grade devices to match the UltraScale+ FPGAs Data Sheet
* Other: Minor revision update for UltraScale+ updates
* Revision change in one or more subcores
UltraScale Soft Error Mitigation (3.1)
* Version 3.1 (Rev. 4)
* Resolved (Xilinx Answer 68939) for XCVU11P and XCVU13P where SEM initialization does not complete
* Resolved (Xilinx Answer 68940) for UltraScale+ SSI devices where status_diagnostic_scan and status_detect_only do not assert under unexpected fatal error conditions
* Resolved (Xilinx Answer 68977) for XCVU13P where the Query command does not return the correct frame data when targeting frames in SLR 3.
UltraScale+ 100G Ethernet Subsystem (2.3)
* Version 2.3
* Port Change: Added gt_powergood, tx_preamblein and rx_preambleout signals access to user
* Port Change: Added ctl_an_fec_25g_rs_request signal when ANLT enabled
* Feature Enhancement: Enabled AXI4-Lite Interface support for TX OTN Configuration
* Other: Kintex/Zynq UltraScale+ -1/-1L devices support for 25G line rate
* Revision change in one or more subcores
UltraScale+ PCI Express Integrated Block (1.2)
* Version 1.2 (Rev. 1)
* Bug Fix: Fixed timing issue related to asynchronous CDC signals.
* Bug Fix: Changed default value of parameter AXISTEN_IF_ENABLE_MSG_ROUTE to 0x2FFFF.
* Feature Enhancement: Added support for xczu27dr-ffvg1517,ffve1156 devices.
* Revision change in one or more subcores
Utility Reduced Logic (2.0)
* Version 2.0 (Rev. 3)
* No changes
Utility Vector Logic (2.0)
* Version 2.0 (Rev. 1)
* No changes
VIO (Virtual Input/Output) (3.0)
* Version 3.0 (Rev. 16)
* XA Zynq UltraScale+ MPSoC device support added
Video Color Space Conversion and Correction (1.0)
* Version 1.0 (Rev. 7)
* Revision change in one or more subcores
Video Deinterlacer (5.0)
* Version 5.0 (Rev. 7)
* Revision change in one or more subcores
Video Frame Buffer Read (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
Video Frame Buffer Write (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
Video Horizontal Chroma Resampler (1.0)
* Version 1.0 (Rev. 7)
* Revision change in one or more subcores
Video Horizontal Scaler (1.0)
* Version 1.0 (Rev. 7)
* Revision change in one or more subcores
Video In to AXI4-Stream (4.0)
* Version 4.0 (Rev. 6)
* No changes
Video Letterbox Engine (1.0)
* Version 1.0 (Rev. 7)
* Revision change in one or more subcores
Video Mixer (1.0)
* Version 1.0 (Rev. 5)
* Revision change in one or more subcores
Video On Screen Display (6.0)
* Version 6.0 (Rev. 13)
* No changes
Video PHY Controller (2.0)
* Version 2.0 (Rev. 6)
* Bug Fix: Implemented control registers for rxpolarity_in, txinhibit_in, txpolarity_in and txpostcursor_in GT ports
* Bug Fix: Implemented status register for rxcdrlock_out GT port
* Bug Fix: Enabled CPLL Calibration block in GTHE4 and added corresponding controlling connections
* Bug Fix: Changed get_pin to get_pins command in XDC
* Bug Fix: Moved RXOUTCLK declaration from clocks XDC to core XDC
Video Processing Subsystem (2.0)
* Version 2.0 (Rev. 5)
* Revision change in one or more subcores
Video Test Pattern Generator (7.0)
* Version 7.0 (Rev. 7)
* Revision change in one or more subcores
Video Timing Controller (6.1)
* Version 6.1 (Rev. 10)
* No changes
Video Vertical Chroma Resampler (1.0)
* Version 1.0 (Rev. 7)
* Revision change in one or more subcores
Video Vertical Scaler (1.0)
* Version 1.0 (Rev. 7)
* Revision change in one or more subcores
Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.2)
* Version 4.2 (Rev. 5)
* Bug Fix: PCI Express Extended Configuration Space Enable parameter enables config extended interface
Viterbi Decoder (9.1)
* Version 9.1 (Rev. 7)
* No changes
XADC Wizard (3.3)
* Version 3.3 (Rev. 3)
* No changes
XAUI (12.3)
* Version 12.3
* Port Change: Added new output port gtpowergood_out
* Other: Changed version of helper core gtwizard_UltraScale from v1_6 to v1_7
XHMC (1.0)
* Version 1.0 (Rev. 3)
* Bug Fix: Fix RTL bug which ignore the ClearErrorAbort bit in the pre-defined IRETRY packet
* Other: Added the support for up-revisioned GTWizard v1_7
* Revision change in one or more subcores
YCrCb to RGB Color-Space Converter (7.1)
* Version 7.1 (Rev. 10)
* No changes
ZYNQ UltraScale+ VCU (1.0)
* Version 1.0
* No changes
ZYNQ7 Processing System (5.5)
* Version 5.5 (Rev. 5)
* No changes
ZYNQ7 Processing System VIP (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
Zynq UltraScale+ MPSoC (3.0)
* Version 3.0 (Rev. 1)
* 1) The maximum frequency for the LPD interconnect is reduced to 260 MHz for ES1 and ES2 Si; A critical warning will be generated for such designs.
* 2) TSU_SIGNALS can be enabled when GEM_PERIPHERAL_IO is on MIO or GT Lane. In order to enable these, use the PS-PL Configuration (General/Others/GEM) in the GUI.
* 3) XA Zynq UltraScale+ MPSoC device support added.
axi_sg (4.1)
* Version 4.1 (Rev. 6)
* No changes
interrupt_controller (3.1)
* Version 3.1 (Rev. 4)
* No changes
lib_bmg (1.0)
* Version 1.0 (Rev. 8)
* No changes
lib_cdc (1.0)
* Version 1.0 (Rev. 2)
* No changes
lib_fifo (1.0)
* Version 1.0 (Rev. 8)
* No changes
lib_pkg (1.0)
* Version 1.0 (Rev. 2)
* No changes
lib_srl_fifo (1.0)
* Version 1.0 (Rev. 2)
* No changes
| AR# 69326 | |
|---|---|
| 日期 | 06/29/2017 |
| 状态 | Active |
| Type | 版本说明 |
| Tools | |