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* Port Change: Enabled the feature related ports
* Feature Enhancement: Initial Release
* Feature Enhancement: 1x100GE core speed support
* Feature Enhancement: 4x25GE core speed support
* Feature Enhancement: 1588 PTP support with 1-step and 2-step
* Feature Enhancement: TX/RX flow control support
* Feature Enhancement: 1x100GE and 4x25GE with FEC configuration support
* Feature Enhancement: Support for AXI4-lite interface
100M/1G TSN Subsystem (2.0)
* Version 2.0 (Rev. 3)
* General: Enabled IP for low-end devices
* Revision change in one or more subcores
10G Ethernet MAC (15.1)
* Version 15.1 (Rev. 7)
* General: Updated to support production silicon for AKINTEX7 devices
10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)
* Version 6.0 (Rev. 15)
* Bug Fix: areset does not toggle qpllreset.
* Bug Fix: Updating of DRP address of RX_PRBS_ERR_CNT for GTYE3.
* Revision change in one or more subcores
10G Ethernet Subsystem (3.1)
* Version 3.1 (Rev. 11)
* Revision change in one or more subcores
10G/25G Ethernet Subsystem (3.0)
* Version 3.0
* Feature Enhancement: Added LPM/DFE mode selection in xxv_ethernet IP
* Feature Enhancement: Added feature enabling AXI4 statistics counter
* Feature Enhancement: Added Versal GTWIZ support
* Feature Enhancement: Updated Auto Negotiation/Link Training Logic Register space bit fields
* Revision change in one or more subcores
1G/10G/25G Switching Ethernet Subsystem (2.3)
* Version 2.3
* Port Change: Added signal_detect, basex_or_sgmii, an_interrupt ports for 1G PCS core
* Bug Fix: Updated for timing DRCs
* Feature Enhancement: Adding support for CL37 AN for 1000BASEX/SGMII. Manual selection between 1G and 10G.
* Feature Enhancement: Added ports for CL37 AN
* Other: added new devices support
* Revision change in one or more subcores
1G/2.5G Ethernet PCS/PMA or SGMII (16.1)
* Version 16.1 (Rev. 6)
* Bug Fix: Updated the reset logic for s_axi_resetn to AXI4 lite IPIF module
* Bug Fix: Updated GUI DRC check for DRP Clock Rate
* Bug Fix: Updated the CDR logic for Master and Slave data read from FIFO for 1000BaseX and SGMII mode for (Xilinx Answer 72084)
* Bug Fix: Updated the fix for auto-neg restart self clear for cl37
* Revision change in one or more subcores
32-bit Initiator/Target for PCI (7 Series) (5.0)
* Version 5.0 (Rev. 12)
* No changes
3GPP LTE Channel Estimator (2.0)
* Version 2.0 (Rev. 16)
* Revision change in one or more subcores
3GPP LTE MIMO Decoder (3.0)
* Version 3.0 (Rev. 15)
* Revision change in one or more subcores
3GPP LTE MIMO Encoder (4.0)
* Version 4.0 (Rev. 14)
* Revision change in one or more subcores
3GPP Mixed Mode Turbo Decoder (2.0)
* Version 2.0 (Rev. 18)
* Bug Fix: Addressing memory leak in MEX wrapper.
* Revision change in one or more subcores
3GPP Turbo Encoder (5.0)
* Version 5.0 (Rev. 15)
* Revision change in one or more subcores
3GPPLTE Turbo Encoder (4.0)
* Version 4.0 (Rev. 15)
* Revision change in one or more subcores
40G/50G Ethernet Subsystem (2.5)
* Version 2.5
* Feature Enhancement: Added feature enabling AXI4 statistics counter
* Feature Enhancement: Added 4x10.3125G with GTM Transceiver
* Feature Enhancement: Added 50G Ethernet Subsystem with GTM transceiver
* Feature Enhancement: Updated Auto Negotiation/Link Training Logic Register space bit fields
* Other: added new devices support
* Revision change in one or more subcores
64-bit Initiator/Target for PCI (7 Series) (5.0)
* Version 5.0 (Rev. 11)
* No changes
7 Series FPGAs Transceivers Wizard (3.6)
* Version 3.6 (Rev. 11)
* General: Added support for xa7k160tffg676-1q device.
7 Series Integrated Block for PCI Express (3.3)
* Version 3.3 (Rev. 11)
* General: Added new device xa7k160t.
AHB-Lite to AXI Bridge (3.0)
* Version 3.0 (Rev. 14)
* General: Updated Example design scripts. No functional changes
* Revision change in one or more subcores
AI Engine (1.0)
* Version 1.0
* No changes
AMM Master Bridge (1.0)
* Version 1.0 (Rev. 5)
* General: Updated Example Design Scripts. No functional changes
* Revision change in one or more subcores
AMM Slave Bridge (1.0)
* Version 1.0 (Rev. 9)
* General: Updated Example Design Scripts. No functional changes
* Revision change in one or more subcores
AXI 1G/2.5G Ethernet Subsystem (7.1)
* Version 7.1 (Rev. 6)
* Feature Enhancement: Added block automation support for VCU128 and VCU129 boards
* Other: Refer to tri_mode_ethernet_mac v9_0 and gig_ethernet_pcs_pma v16_1 core change logs for changes in the sub cores of this core
* Revision change in one or more subcores
AXI AHBLite Bridge (3.0)
* Version 3.0 (Rev. 16)
* General: Updated Example design scripts. No functional changes
* Revision change in one or more subcores
AXI APB Bridge (3.0)
* Version 3.0 (Rev. 15)
* General: Minor updates to example design of the IP
AXI BRAM Controller (4.1)
* Version 4.1 (Rev. 1)
* Feature Enhancement: Read Latency Support added
* Feature Enhancement: ECC bits organization logic retained for all devices
* Feature Enhancement: Read Command Optimization Parameter added to Optimize the Read Command latency
* Other: BMG support removed and corresponding parameter to select between BMG and XPM also removed
AXI Bridge for PCI Express Gen3 Subsystem (3.0)
* Version 3.0 (Rev. 9)
* Feature Enhancement: Added GUI option to disable the GT channel LOC constraints in GTWizard IP XDC
* Feature Enhancement: Added GUI option MCAP_FPGA_BITSTREAM_VERSION for TANDEM
* Revision change in one or more subcores
AXI CAN (5.0)
* Version 5.0 (Rev. 22)
* General: Example design updated to support Versal Devices
* Revision change in one or more subcores
AXI Central Direct Memory Access (4.1)
* Version 4.1 (Rev. 19)
* General: Enhanced support for IP Integrator
* Revision change in one or more subcores
AXI Chip2Chip Bridge (5.0)
* Version 5.0 (Rev. 5)
* General: Migrated Aurora 64B66B subcore from 11.2 to 12.0.
* Revision change in one or more subcores
AXI Clock Converter (2.1)
* Version 2.1 (Rev. 18)
* General: remove support for Versal
* Revision change in one or more subcores
AXI Crossbar (2.1)
* Version 2.1 (Rev. 20)
* General: Hide support for Versal
* Revision change in one or more subcores
AXI Data FIFO (2.1)
* Version 2.1 (Rev. 18)
* General: remove support for Versal
* Revision change in one or more subcores
AXI Data Width Converter (2.1)
* Version 2.1 (Rev. 19)
* General: remove support for Versal
* Revision change in one or more subcores
AXI DataMover (5.1)
* Version 5.1 (Rev. 21)
* General: Updates to example design
* Revision change in one or more subcores
AXI Direct Memory Access (7.1)
* Version 7.1 (Rev. 20)
* General: Implemented new XDC waiver mechanism to mask user visibility of acceptable warnings
* Revision change in one or more subcores
AXI EMC (3.0)
* Version 3.0 (Rev. 19)
* General: Updates to example design. No functional changes
* Revision change in one or more subcores
AXI EPC (2.0)
* Version 2.0 (Rev. 22)
* General: No Functional changes
* Revision change in one or more subcores
AXI Ethernet Buffer (2.0)
* Version 2.0 (Rev. 20)
* Revision change in one or more subcores
AXI Ethernet Clocking (2.0)
* Version 2.0 (Rev. 2)
* No changes
AXI EthernetLite (3.0)
* Version 3.0 (Rev. 17)
* Revision change in one or more subcores
AXI GPIO (2.0)
* Version 2.0 (Rev. 21)
* General: No Functional changes
* Revision change in one or more subcores
AXI HWICAP (3.0)
* Version 3.0 (Rev. 23)
* General: No Functional changes
* Revision change in one or more subcores
AXI IIC (2.0)
* Version 2.0 (Rev. 22)
* General: No Functional changes
* Revision change in one or more subcores
AXI Interconnect (2.1)
* Version 2.1 (Rev. 20)
* General: remove support for Versal
* Revision change in one or more subcores
AXI Interrupt Controller (4.1)
* Version 4.1 (Rev. 13)
* General: Update parameters C_DISABLE_SYNCHRONIZERS and C_MB_CLK_NOT_CONNECTED when C_HAS_FAST is changed
AXI Lite IPIF (3.0)
* Version 3.0 (Rev. 4)
* No changes
AXI MMU (2.1)
* Version 2.1 (Rev. 17)
* General: Hide support for Versal
* Revision change in one or more subcores
AXI Master Burst (2.0)
* Version 2.0 (Rev. 7)
* No changes
AXI Memory Init (1.0)
* Version 1.0
* Native Vivado Release
* Initial release.
AXI Memory Mapped To PCI Express (2.9)
* Version 2.9 (Rev. 1)
* Feature Enhancement: Added support for device xa7k160t
* Feature Enhancement: Support of CPG236/CPG238 re-established for x2 modes
* Revision change in one or more subcores
AXI Memory Mapped to Stream Mapper (1.1)
* Version 1.1 (Rev. 18)
* Revision change in one or more subcores
AXI Multi Channel Direct Memory Access (1.1)
* Version 1.1
* General: TID behavior changed. It remains constant throughout packet length.
* Revision change in one or more subcores
AXI Performance Monitor (5.0)
* Version 5.0 (Rev. 21)
* General: No Functional changes
* Revision change in one or more subcores
AXI Protocol Checker (2.0)
* Version 2.0 (Rev. 5)
* General: clocking wizard update for Versal support
* Revision change in one or more subcores
AXI Protocol Converter (2.1)
* Version 2.1 (Rev. 19)
* General: remove support for Versal
* Revision change in one or more subcores
AXI Protocol Firewall (1.0)
* Version 1.0 (Rev. 7)
* General: Package change for simulation sources.
* Revision change in one or more subcores
AXI Quad SPI (3.2)
* Version 3.2 (Rev. 18)
* General: Internal GUI changes and New commands support for Micron and added Macronix feature.
* Revision change in one or more subcores
AXI Register Slice (2.1)
* Version 2.1 (Rev. 19)
* New Feature: Added auto-pipelining mode to automatically insert timing-driven pipeline stages to improve QOR of SLR-crossings.
* Other: Extended AXI Metadata added
* Revision change in one or more subcores
AXI Sideband Utility (1.0)
* Version 1.0 (Rev. 3)
* General: clocking wizard update for Versal support
* Revision change in one or more subcores
AXI SmartConnect (1.0)
* Version 1.0 (Rev. 11)
* Feature Enhancement: Low area mode optimization for clock conversion and splitting
* Revision change in one or more subcores
AXI TFT Controller (2.0)
* Version 2.0 (Rev. 22)
* General: Added Waiver for Timing 14. No Functional changes
* Revision change in one or more subcores
AXI Timebase Watchdog Timer (3.0)
* Version 3.0 (Rev. 11)
* Feature Enhancement: No Functional changes
* Revision change in one or more subcores
AXI Timer (2.0)
* Version 2.0 (Rev. 21)
* General: No Functional changes
* Revision change in one or more subcores
AXI Traffic Generator (3.0)
* Version 3.0 (Rev. 5)
* General: Fixed GUI in HLT mode
* Revision change in one or more subcores
AXI UART16550 (2.0)
* Version 2.0 (Rev. 21)
* General: No Functional changes
* Revision change in one or more subcores
AXI USB2 Device (5.0)
* Version 5.0 (Rev. 20)
* General: Added IP Waiver Mechanism. No Functional changes
* Revision change in one or more subcores
AXI Uartlite (2.0)
* Version 2.0 (Rev. 23)
* General: No Functional changes
* Revision change in one or more subcores
AXI Verification IP (1.1)
* Version 1.1 (Rev. 5)
* General: update to have has_size
* Revision change in one or more subcores
AXI Video Direct Memory Access (6.3)
* Version 6.3 (Rev. 7)
* General: Implemented new XDC waiver mechanism to mask user visibility of acceptable warnings
* General: Added Versal support
* Revision change in one or more subcores
AXI Virtual FIFO Controller (2.0)
* Version 2.0 (Rev. 21)
* General: Internal device family change, no functional changes
* Revision change in one or more subcores
AXI-Stream FIFO (4.2)
* Version 4.2 (Rev. 1)
* Revision change in one or more subcores
AXI4 Debug Hub (1.0)
* Version 1.0
* No changes
AXI4-Stream Accelerator Adapter (2.1)
* Version 2.1 (Rev. 15)
* General: Waivers added in the constraints file. No functional changes
AXI4-Stream Broadcaster (1.1)
* Version 1.1 (Rev. 18)
* General: Replace old clock API with get_datetime.
* Revision change in one or more subcores
AXI4-Stream Clock Converter (1.1)
* Version 1.1 (Rev. 20)
* Revision change in one or more subcores
AXI4-Stream Combiner (1.1)
* Version 1.1 (Rev. 17)
* Revision change in one or more subcores
AXI4-Stream Data FIFO (2.0)
* Version 2.0 (Rev. 1)
* Port Change: Corrected the port crossovers of biterr injections for xpm
* Revision change in one or more subcores
AXI4-Stream Data Width Converter (1.1)
* Version 1.1 (Rev. 18)
* Revision change in one or more subcores
AXI4-Stream ILA (Integrated Logic Analyzer) (1.0)
* Version 1.0
* Native Vivado Release
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
AXI4-Stream Interconnect (2.1)
* Version 2.1 (Rev. 20)
* Revision change in one or more subcores
AXI4-Stream Protocol Checker (2.0)
* Version 2.0 (Rev. 3)
* Revision change in one or more subcores
AXI4-Stream Register Slice (1.1)
* Version 1.1 (Rev. 19)
* General: axi_traffic_gen update from v2.0 to v3.0
* Revision change in one or more subcores
AXI4-Stream Subset Converter (1.1)
* Version 1.1 (Rev. 19)
* General: Replace old clock API with get_datetime.
* Revision change in one or more subcores
AXI4-Stream Switch (1.1)
* Version 1.1 (Rev. 19)
* Revision change in one or more subcores
AXI4-Stream VIO (Virtual Input/Output) (1.0)
* Version 1.0
* New Release
AXI4-Stream Verification IP (1.1)
* Version 1.1 (Rev. 5)
* General: update to honor user parameters user strength in slave mode
* Revision change in one or more subcores
AXI4-Stream to Video Out (4.0)
* Version 4.0 (Rev. 10)
* No changes
Accumulator (12.0)
* Version 12.0 (Rev. 13)
* General: support for new devices. No change to functionality.
* Revision change in one or more subcores
Adder/Subtracter (12.0)
* Version 12.0 (Rev. 13)
* General: Support for new devices. No change to existing functionality, resource use or performance.
* Revision change in one or more subcores
Advanced IO Wizard (1.0)
* Version 1.0
* No changes
Audio Clock Recovery Unit (1.0)
* Version 1.0 (Rev. 1)
* No changes
Audio Formatter (1.0)
* Version 1.0 (Rev. 1)
* General: Minor non-functional changes in example design
* General: Added Versal support
* Revision change in one or more subcores
Aurora 64B66B (12.0)
* Version 12.0
* General: Added support for Versal devices
* General: Added support for AKINTEX7 devices
* Revision change in one or more subcores
Aurora 8B10B (11.1)
* Version 11.1 (Rev. 7)
* General: Added support for AKINTEX7 devices
* Revision change in one or more subcores
Binary Counter (12.0)
* Version 12.0 (Rev. 13)
* General: support for new devices. No change to functionality.
* Revision change in one or more subcores
Block Memory Generator (8.4)
* Version 8.4 (Rev. 3)
* General: Internal device family change, no functional changes
CANFD (2.0)
* Version 2.0 (Rev. 1)
* General: Example Design updated to support Versal devices
* Revision change in one or more subcores
CIC Compiler (4.0)
* Version 4.0 (Rev. 14)
* General: Addressing DRC warning in comb.
* Revision change in one or more subcores
CORDIC (6.0)
* Version 6.0 (Rev. 15)
* Bug Fix: Fixed C model crash when multiple DSP IP C models are run together: See (Xilinx Answer 71876)
* Revision change in one or more subcores
CPRI (8.10)
* Version 8.10
* Port Change: Added optional Structure Agnostic Line Coding Aware interface ports.
* Feature Enhancement: Added optional Structure Agnostic Line Coding Aware Mode.
* Feature Enhancement: Added extended CDC FIFO depth to support long transmission lines.
* Revision change in one or more subcores
Card Management Solution Subsystem (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
Chroma Resampler (4.0)
* Version 4.0 (Rev. 14)
* No changes
Clock Verification IP (1.0)
* Version 1.0 (Rev. 2)
* No changes
Clocking Wizard (6.0)
* Version 6.0 (Rev. 3)
* Bug Fix: Internal GUI fixes
* Other: New family support added
Color Correction Matrix (6.0)
* Version 6.0 (Rev. 15)
* No changes
Color Filter Array Interpolation (7.0)
* Version 7.0 (Rev. 14)
* No changes
Compact GT (1.0)
* Version 1.0 (Rev. 5)
* Revision change in one or more subcores
Complex Multiplier (6.0)
* Version 6.0 (Rev. 17)
* Bug Fix: Fixed C model crash when multiple DSP IP C models are run together: See (Xilinx Answer 71876)
* Revision change in one or more subcores
Concat (2.1)
* Version 2.1 (Rev. 3)
* Add get_display_strings to bd/bd.tcl.
Constant (1.1)
* Version 1.1 (Rev. 6)
* Add bd/bd.tcl to provide get_display_strings.
Control, Interface & Processing System (1.0)
* Version 1.0
* No changes
Convolution Encoder (9.0)
* Version 9.0 (Rev. 14)
* Revision change in one or more subcores
DDR3 SDRAM (MIG) (1.4)
* Version 1.4 (Rev. 7)
* General: Updated for 2019.1
* Revision change in one or more subcores
DDR4 SDRAM (MIG) (2.2)
* Version 2.2 (Rev. 7)
* General: Updated for 2019.1
* Revision change in one or more subcores
DDS Compiler (6.0)
* Version 6.0 (Rev. 18)
* Bug Fix: Addressing memory leak in MEX wrapper.
* Bug Fix: Fixed C model crash when multiple DSP IP C models are run together: See (Xilinx Answer 71876)
* Revision change in one or more subcores
DMA/Bridge Subsystem for PCI Express (PCIe) (4.1)
* Version 4.1 (Rev. 3)
* Bug Fix: Fixed core generation issue for -1M device with Gen2 and 125 MHz AXI clock frequency.
* Bug Fix: Fixed back to back reads failure for 7 Series Gen2 DMA.
* Feature Enhancement: Added GUI option to disable the GT channel LOC constraints in GTWizard IP XDC
* Revision change in one or more subcores
DSP Macro (1.0)
* Version 1.0
* New Feature: Squaring operations from the result of the preadder supported for UltraScale and Versal
* Other: Initial release of DSP Macro. This core supersedes DSP48 Macro (xbip_dsp48_macro).
* Other: Support for Versal devices (DSP58/DSP Engine)
* Other: Improved GUI error handling
* Other: Improved full precision output (P) width calculation. Preadder additions now increase full precision width appropriately.
DSP48 Macro (3.0)
* Version 3.0 (Rev. 17)
* Revision change in one or more subcores
DUC/DDC Compiler (3.0)
* Version 3.0 (Rev. 15)
* General: Rephrase of code to overcome warning about doubly-driven signal. No change to functionality or performance.
* Revision change in one or more subcores
Debug Bridge (3.0)
* Version 3.0 (Rev. 5)
* General: Updated the waivers for CDC
* Revision change in one or more subcores
Discrete Fourier Transform (4.1)
* Version 4.1 (Rev. 1)
* Revision change in one or more subcores
DisplayPort (9.0)
* Version 9.0 (Rev. 1)
* Revision change in one or more subcores
DisplayPort RX Subsystem (2.1)
* Version 2.1 (Rev. 5)
* Bug Fix: AXI VDMA configuration update in KCU105 Pass-through example design
* Bug Fix: Updated the 0x0A and 0x0B DPCD registers when Audio is enabled
* Bug Fix: Added ALMOST FULL pin to HDCP Egress and Ingress FIFOs. It is used to avoid data corruption when HDCP 1.3/HDCP 2.2 is enabled
* Revision change in one or more subcores
DisplayPort TX Subsystem (2.1)
* Version 2.1 (Rev. 5)
* Bug Fix: AXI VDMA configuration update in KCU105 Pass-through example design
* Bug Fix: Added 0x090 AXI-4 Lite register to fine tune MVID[7:0] value
* Bug Fix: Added ALMOST FULL pin to HDCP Egress and Ingress FIFOs. It is used to avoid data corruption when HDCP 1.3/HDCP 2.2 is enabled
* Revision change in one or more subcores
Distributed Memory Generator (8.0)
* Version 8.0 (Rev. 13)
* General: Internal device family change, no functional changes
Divider Generator (5.1)
* Version 5.1 (Rev. 15)
* Bug Fix: Addressing memory leak in MEX wrapper.
* Bug Fix: Fixed C model crash when multiple DSP IP C models are run together: See (Xilinx Answer 71876)
* Revision change in one or more subcores
Double Data Rate Sampling (1.0)
* Version 1.0
* No changes
ECC (2.0)
* Version 2.0 (Rev. 13)
* General: Example design updated to use latest clocking wizard, and no functional change in the core.
ERNIC (1.0)
* Version 1.0 (Rev. 1)
* Bug Fix: Issue in the QP ID field of read response packet is fixed
* Other: Performance improvement
* Revision change in one or more subcores
ETRNIC (1.1)
* Version 1.1 (Rev. 2)
* Revision change in one or more subcores
Ethernet PHY MII to Reduced MII (2.0)
* Version 2.0 (Rev. 21)
* General: This IP will be deprecated from 2019.2 release onwards. Please contact your Xilinx FAE if you are looking for this IP
* Revision change in one or more subcores
FEC 5G Common Utilities (1.1)
* Version 1.1 (Rev. 1)
* Revision change in one or more subcores
FIFO Generator (13.2)
* Version 13.2 (Rev. 4)
* Bug Fix: Destination Clock not connected properly for some XPM_CDC instances when in common clock mode. Conditions added to connect the correct clock
* Other: IP Waivers added in constraint files. No functional changes
* Revision change in one or more subcores
FIR Compiler (7.2)
* Version 7.2 (Rev. 12)
* Bug Fix: Addressing memory leak in MEX wrapper.
* Bug Fix: Fixed coefficient width range minimum for coefficient file input.
* Bug Fix: Fixed upper bound of Sample Frequency when Advanced Channel Sequence is selected.
* Bug Fix: Fixed C model crash when multiple DSP IP C models are run together: see (Xilinx Answer 71876)
* Other: Support for new devices. No change to existing functionality, resource use or performance.
* Revision change in one or more subcores
Fast Fourier Transform (9.1)
* Version 9.1 (Rev. 2)
* General: support for new devices. No change to functionality.
* Revision change in one or more subcores
Fiber Channel 32GFC RS-FEC (1.0)
* Version 1.0 (Rev. 10)
* General: Device support updated, including Versal devices
* Revision change in one or more subcores
Fixed Interval Timer (2.0)
* Version 2.0 (Rev. 10)
* General: Updated to support Versal.
FlexO 100G RS-FEC (1.0)
* Version 1.0 (Rev. 10)
* General: Device support updated, including Versal devices
* Revision change in one or more subcores
Floating-point (7.1)
* Version 7.1 (Rev. 8)
* General: support for new devices. No change to functionality.
* Revision change in one or more subcores
G.709 FEC Encoder/Decoder (2.4)
* Version 2.4 (Rev. 1)
* General: Added support for new devices. No changes to interfaces, form or functionality
* Revision change in one or more subcores
G.975.1 EFEC I.4 Encoder/Decoder (1.0)
* Version 1.0 (Rev. 17)
* Revision change in one or more subcores
G.975.1 EFEC I.7 Encoder/Decoder (2.0)
* Version 2.0 (Rev. 18)
* Revision change in one or more subcores
Gamma Correction (7.0)
* Version 7.0 (Rev. 15)
* No changes
Gamma LUT (1.0)
* Version 1.0 (Rev. 5)
* General: Added Versal support.
* Revision change in one or more subcores
GMII to RGMII (4.0)
* Version 4.0 (Rev. 7)
* No changes
HBM IP (1.0)
* Version 1.0 (Rev. 3)
* General: Updated for 2019.1
HDCP (1.0)
* Version 1.0 (Rev. 3)
* No changes
HDCP 2.2 Cipher (1.0)
* Version 1.0 (Rev. 3)
* No changes
HDCP 2.2 Cipher for DP (1.0)
* Version 1.0
* Initial release
HDCP 2.2 Montgomery Modular Multiplier (1.0)
* Version 1.0 (Rev. 2)
* No changes
HDCP 2.2 Random Number Generator (1.0)
* Version 1.0 (Rev. 1)
* No changes
HDCP 2.2 Receiver (1.0)
* Version 1.0 (Rev. 11)
* Revision change in one or more subcores
HDCP 2.2 Receiver for DisplayPort 1.4 Subsystems (1.0)
* Version 1.0
* Initial release
* Support for receiver mode
* No support for repeater or converter mode upstream interface
HDCP 2.2 Transmitter (1.0)
* Version 1.0 (Rev. 11)
* Revision change in one or more subcores
HDCP 2.2 Transmitter for DisplayPort 1.4 Subsystem (1.0)
* Version 1.0
* Initial release
* Support for DP protocol
* Support for transmitter mode
* No support for repeater or converter mode downstream interface
HDMI 1.4/2.0 Receiver (3.0)
* Version 1.1
* No changes
HDMI 1.4/2.0 Receiver Subsystem (3.1)
* Version 3.1 (Rev. 2)
* Bug Fix: Fixed Type mismatch between connected pins Warning in Example Design
* Bug Fix: Fixed No cells matched warning caused by constraints in hdmi_acr_ctrl.xdc and AudioGen.xdc in Example Design
* Feature Enhancement: Added support for Virtex UltraScale+ 58g and Virtex UltraScale+ HBM Devices
* Feature Enhancement: Enhanced AUX packet FIFO reading mechanism
* Revision change in one or more subcores
HDMI 1.4/2.0 Transmitter (3.0)
* Version 2.0
* No changes
HDMI 1.4/2.0 Transmitter Subsystem (3.1)
* Version 3.1 (Rev. 2)
* Feature Enhancement: Added support for Virtex UltraScale+ 58g and Virtex UltraScale+ HBM Devices
* Feature Enhancement: Enhanced TX HPD timer mechanism to avoid overrun upon startup
* Revision change in one or more subcores
HDMI GT Controller (1.0)
* Version 1.0
* General: Initial version
* General: Supports Versal Family Only
* General: Supports HDMI 1.4/2.0 and HDMI 2.1 Subsystem IPs
* General: Supports GTYE5 Transceiver only
High Speed SelectIO Wizard (3.5)
* Version 3.5 (Rev. 1)
* General: Bug fixes in Asynchronous Time mode.
I2S Receiver (1.0)
* Version 1.0 (Rev. 3)
* General: Updates to Example Design. I2S RX and TX both use the Master Mode.
* General: Added Versal support
* Revision change in one or more subcores
I2S Transmitter (1.0)
* Version 1.0 (Rev. 3)
* General: Updates to Example Design. I2S RX and TX both use the Master Mode.
* General: Added Versal support
* Revision change in one or more subcores
IBERT 7 Series GTH (3.0)
* Version 3.0 (Rev. 18)
* General: Updated device support
IBERT 7 Series GTP (3.0)
* Version 3.0 (Rev. 18)
* General: Updated device support list.
IBERT 7 Series GTX (3.0)
* Version 3.0 (Rev. 18)
* General: Added support for automotive Kintex device
IBERT 7 Series GTZ (3.1)
* Version 3.1 (Rev. 17)
* General: Updated device support
* Revision change in one or more subcores
IBERT UltraScale GTH (1.4)
* Version 1.4 (Rev. 2)
* General: Updated device support
* Revision change in one or more subcores
IBERT UltraScale GTM (1.0)
* Version 1.0 (Rev. 1)
* New Feature: Added support for NRZ modulation.
* Revision change in one or more subcores
IBERT UltraScale GTY (1.3)
* Version 1.3 (Rev. 2)
* General: Added device support for GTY devices
* Revision change in one or more subcores
IEEE 802.3 200G RS-FEC (1.0)
* Version 1.0 (Rev. 6)
* General: Device support updated, including Versal devices
* Revision change in one or more subcores
IEEE 802.3 25G RS-FEC (1.0)
* Version 1.0 (Rev. 12)
* General: User can now generate only TX and/or RX. By default, both sides are enabled. No changes required by the user.
* General: Device support expanded to include Versal devices.
* Revision change in one or more subcores
IEEE 802.3 400G RS-FEC (1.0)
* Version 1.0 (Rev. 6)
* General: Device support updated, including Versal devices
* Revision change in one or more subcores
IEEE 802.3 50G RS-FEC (2.0)
* Version 2.0
* General: Added KP4 mode and updated device support, including Versal devices.
* Revision change in one or more subcores
IEEE 802.3 Clause 74 FEC (1.0)
* Version 1.0 (Rev. 4)
* General: Device support updated, including Versal devices
* Revision change in one or more subcores
IEEE 802.3 Multi-channel 25G RSFEC (1.0)
* Version 1.0 (Rev. 2)
* General: Device support updated, including Versal devices
* General: Updated cmac_usplus version number
IEEE 802.3bj 100G RS-FEC (2.0)
* Version 2.0 (Rev. 4)
* General: Device support updated, including Versal devices. Example design updated for UltraScale+.
* Revision change in one or more subcores
ILA (Integrated Logic Analyzer) (6.2)
* Version 6.2 (Rev. 9)
* General: Updated the waivers for CDC
* Revision change in one or more subcores
IOModule (3.1)
* Version 3.1 (Rev. 4)
* No changes
Image Enhancement (8.0)
* Version 8.0 (Rev. 15)
* No changes
In System IBERT (1.0)
* Version 1.0 (Rev. 9)
* Revision change in one or more subcores
Interlaken 150G (2.4)
* Version 2.4 (Rev. 3)
* Bug Fix: Updated Board Tab visibility for VCU108 board
* Revision change in one or more subcores
Interleaver/De-interleaver (8.0)
* Version 8.0 (Rev. 14)
* Revision change in one or more subcores
JESD204 (7.2)
* Version 7.2 (Rev. 6)
* Revision change in one or more subcores
JESD204 PHY (4.0)
* Version 4.0 (Rev. 6)
* Bug Fix: Changed the sync header alignment algorithm for 64B66B to prevent locking to an incorrect position if a valid header is received in the same clock cycle as the FSM moves from SH_LOCK to SH_INIT
* Feature Enhancement: Changed the conditions to move from SH_LOCK to SH_INIT in the sync header alignment algorithm for 64B66B to make the process more robust
* Feature Enhancement: Removed calls to the Tcl clock procedure from all source files to speed up design processing
* Other: TBD
* Revision change in one or more subcores
JESD204C (4.1)
* Version 4.1
* Bug Fix: Fixed issue in 64B66B RX core where loss of EMB_LOCK would not reliably force a complete resync.
* Feature Enhancement: Increased the accuracy of the clocks in the IP example design.
* Feature Enhancement: Improved the readability of the IP example design.
* Feature Enhancement: Added a new feature to register CTRL_SYSREF at address 0x50. Bits 8, 9 and 10 are now used to specify a tolerance value to sysref detection in sysref always mode (default value 0).
If sysref is within the tolerance with respect to its expected position, no error is issued. See (PG242).
* Feature Enhancement: For 64B66B cores only. The number of core clock cycles SYSREF can be delayed for has been increased from 15 to 255. Bits 16 to 23 of CTRL_SYSREF are now used to configure this value.
* Feature Enhancement: Removed calls to the Tcl clock procedure from all source files to speed up design processing
* Feature Enhancement: Added a new feature to per lane registers CTRL_TX_ILA_LID. Bits 16-20 of these registers are now used to specify the lanes per link for each lane (write no. lanes - 1).
The default value for these registers is the number of lanes the core was initially configured to have minus one (see PG-242).
* Feature Enhancement: Enhanced 64B66B RX core such that when an alignment buffer overflow occurs the core will not output data.
* Feature Enhancement: Enhanced 64B66B RX core to start LEMC in subclass 0 based on received link timing.
* Other: TBD
* Revision change in one or more subcores
JTAG to AXI Master (1.2)
* Version 1.2 (Rev. 9)
* General: Added support for automotive Kintex device
* Revision change in one or more subcores
LDPC Encoder/Decoder (2.0)
* Version 2.0 (Rev. 3)
* Bug Fix: Correction to transaction file generation on Windows.
* Bug Fix: Addressing memory leak in MEX wrapper.
* Bug Fix: Add DOCSIS ranging codes.
* Bug Fix: Fixed C model crash when multiple DSP IP C models are run together: (Xilinx Answer 71876)
* Revision change in one or more subcores
LMB BRAM Controller (4.0)
* Version 4.0 (Rev. 16)
* General: Supported devices and production status are now determined automatically, to simplify support for future devices
LPDDR3 SDRAM (MIG) (1.0)
* Version 1.0 (Rev. 7)
* General: Changes for 2019.1
* Revision change in one or more subcores
LTE DL Channel Encoder (4.0)
* Version 4.0
* General: Comment Major update to include full AXI-S and Axi4 interfaces, plus additional hardware to process SCH channel at higher bandwidth.
* Revision change in one or more subcores
LTE Fast Fourier Transform (2.1)
* Version 2.1
* General: Support added for point sizes 384, 768, 3072 and 4096. Arbitrary length cyclic prefix added.
* Revision change in one or more subcores
LTE PUCCH Receiver (2.0)
* Version 2.0 (Rev. 16)
* General: support for new devices. No change to functionality.
* Revision change in one or more subcores
LTE RACH Detector (3.1)
* Version 3.1 (Rev. 5)
* General: support for new devices. No change to functionality.
* Revision change in one or more subcores
LTE UL Channel Decoder (4.0)
* Version 4.0 (Rev. 16)
* Bug Fix: Addressing memory leak in MEX wrapper.
* Revision change in one or more subcores
Local Memory Bus (LMB) 1.0 (3.0)
* Version 3.0 (Rev. 9)
* No changes
MIPI CSI-2 Rx Controller (1.0)
* Version 1.0 (Rev. 8)
* No changes
MIPI CSI-2 Rx Subsystem (4.0)
* Version 4.0 (Rev. 1)
* Bug Fix: RAW20 data corruption issue fixed
* Other: Added support for Versal devices
* Revision change in one or more subcores
MIPI CSI-2 Tx Controller (1.0)
* Version 1.0 (Rev. 4)
* No changes
MIPI CSI-2 Tx Subsystem (2.0)
* Version 2.0 (Rev. 5)
* New Feature: Added example design
* Revision change in one or more subcores
MIPI D-PHY (4.1)
* Version 4.1 (Rev. 3)
* General: Added support for Versal devices
* Revision change in one or more subcores
MIPI DSI Tx Controller (1.0)
* Version 1.0 (Rev. 7)
* No changes
MIPI DSI Tx Subsystem (2.0)
* Version 2.0 (Rev. 5)
* General: Added support for Versal devices
* Revision change in one or more subcores
Mailbox (2.1)
* Version 2.1 (Rev. 11)
* No changes
Mammoth Transcoder (1.0)
* Version 1.0
* No changes
Memory Helper Core (1.4)
* Version 1.4
* No changes
Memory Interface Generator (MIG 7 Series) (4.2)
* Version 4.2 (Rev. 1)
* General: Vivado 2019.1 software support.
MicroBlaze (11.0)
* Version 11.0 (Rev. 1)
* Bug Fix: Avoid synthesis error for instruction victim cache. Versions that have this issue: 7.30.a - 11.0. Can only occur with area or performance optimization when instruction victim cache is enabled, and instruction cache and external memory sizes are equal.
* Other: Supported devices and production status are now determined automatically, to simplify support for future devices
* Other: Updated waivers to add tag. No functional changes.
* Other: Improved compatibility of 64-bit mode instructions
MicroBlaze Debug Module (MDM) (3.2)
* Version 3.2 (Rev. 16)
* General: Updated waivers to add tag. No functional changes.
MicroBlaze MCS (3.0)
* Version 3.0 (Rev. 11)
* General: Supported devices and production status are now determined automatically, to simplify support for future devices
* Revision change in one or more subcores
Multiplier (12.0)
* Version 12.0 (Rev. 15)
* Revision change in one or more subcores
Multiply Adder (3.0)
* Version 3.0 (Rev. 14)
* General: support for new devices. No change to functionality.
* Revision change in one or more subcores
Mutex (2.1)
* Version 2.1 (Rev. 10)
* No changes
NVMe Host Accelerator (1.0)
* Version 1.0
* Feature Enhancement: Made Software AXI interface 32/64 bit configurable to reduce delays
* Other: First Public Release of IP. The component name of this IP in 2018.3 was nvmehc. It has been renamed as nvmeha in the 2019.1 release
NoC Clock Re-Convergent Buffer (1.0)
* Version 1.0
* Internal Release
NoC NIDB (1.0)
* Version 1.0
* No changes
NoC Packet Switch (1.0)
* Version 1.0
* No changes
PCIe PHY IP (1.0)
* Version 1.0 (Rev. 11)
* Bug Fix: Implemented IP waiver mechanism for warnings
* Revision change in one or more subcores
PR AXI Shutdown Manager (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
PR Bitstream Monitor (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
Partial Reconfiguration Controller (1.3)
* Version 1.3 (Rev. 2)
* Revision change in one or more subcores
Partial Reconfiguration Decoupler (1.0)
* Version 1.0 (Rev. 7)
* No changes
Peak Cancellation Crest Factor Reduction (6.3)
* Version 6.3
* Feature Enhancement: LUT optimization for CPS=2 case
* Feature Enhancement: Latency update after LUT optimization for CPS=2 cases only
* Revision change in one or more subcores
Polar Encoder/Decoder (1.0)
* Version 1.0 (Rev. 3)
* Bug Fix: Improvement of error correction performance
* Bug Fix: Correction to code generation function for shortened codes of 512 or longer.
* Bug Fix: Fixed C model crash when multiple DSP IP C models are run together: (Xilinx Answer 71876)
* Revision change in one or more subcores
Processor System Reset (5.0)
* Version 5.0 (Rev. 13)
* No changes
QDRII+ SRAM (MIG) (1.4)
* Version 1.4 (Rev. 7)
* General: Updated for 2019.1
* Revision change in one or more subcores
QDRIV SRAM (MIG) (2.0)
* Version 2.0 (Rev. 7)
* General: Updated for 2019.1
* Revision change in one or more subcores
QDRIV SRAM PHY IP (2.0)
* Version 1.2
* No changes
QSGMII (3.4)
* Version 3.4 (Rev. 6)
* General: Support for zqzu29dr devices
* Revision change in one or more subcores
Queue DMA Subsystem for PCI Express (PCIe) (3.0)
* Version 3.0 (Rev. 1)
* Bug Fix: Removed unused output port axis_c2h_status_imm_or_marker
* Bug Fix: usr_irq_in_vec input port width changed to 5 bits
* Bug Fix: Mailbox interrupts were generated only from PF vectors and not able to generate from other vectors
* Bug Fix: Interrupts not received properly when there is mix of direct interrupts and indirect interrupts
* Bug Fix: AXI-MM only with completion option not working
* Bug Fix: Write back coalesce buffer depth of 32 and 64 not working; issue with depth of 32 is fixed, depth of 64 is not allowed
* Bug Fix: Prefetch cache depth GUI parameter propagation issue
* Bug Fix: C2H write back timer deletion issue: Injection of a timer immediately after deletion causes deletion to stall resulting in multiple timers
* Bug Fix: Marker response not working when queue is disabled
* Bug Fix: Issue with more than 8 interrupt vectors per function using Tcl option CONFIG.adv_int_usr
* Bug Fix: Expansion ROM space (EPROM option selected in last BAR) read/write access issue
* Bug Fix: Example design issue: Completions are not received for ST C2H transfers which follows mix payload transfers (immediate data and payload data)
* Bug Fix: Removed empty cycle after SOP in C2H DMA write engine to improve performance
* Bug Fix: fix for tm_dsc_sts_rdy back pressure issues
* Feature Enhancement: Enabled slot clock configuration option in the GUI
* Feature Enhancement: Enabled support for JTAG debugger and IBERT debug options
* Feature Enhancement: Enabled Shared logic GUI page
* Feature Enhancement: User configurable number of queues 1 to 2048
* Feature Enhancement: Added user parameters for CQ outstanding transactions
* Revision change in one or more subcores
RAM-based Shift Register (12.0)
* Version 12.0 (Rev. 13)
* Revision change in one or more subcores
RAMA IP (1.1)
* Version 1.1 (Rev. 1)
* Timing Improvements.
* Revision change in one or more subcores
RGB to YCrCb Color-Space Converter (7.1)
* Version 7.1 (Rev. 13)
* No changes
RLDRAM3 (MIG) (1.4)
* Version 1.4 (Rev. 7)
* General: Updated for 2019.1
* Revision change in one or more subcores
RXAUI (4.4)
* Version 4.4 (Rev. 6)
* General: Support for zqzu29dr devices
* General: This IP will be deprecated from the 2019.2 release onwards. Please contact your Xilinx FAE if you are looking for this IP.
* Revision change in one or more subcores
Radio over Ethernet Framer (2.0)
* Version 2.0
* General: Early Beta support for ORAN Message Parsing
* General: Legacy version. Modified buffer manager to handle missing or delayed packets in time domain application.
* General: Legacy version. Added 1 clock cycle delay on reading acknowledge signal to avoid issues arising with user clock faster than internal.
* General: Legacy version. Removed issues causing misalignment in the framer output FIFO.
* General: Legacy version. Modifications of framer output FIFO configuration to avoid unsupported parameter assignments.
* General: Legacy version. Modifications of framer data FIFO configuration to assign correct dimension in time domain mode.
Reed-Solomon Decoder (9.0)
* Version 9.0 (Rev. 16)
* Revision change in one or more subcores
Reed-Solomon Encoder (9.0)
* Version 9.0 (Rev. 15)
* Revision change in one or more subcores
Reset Verification IP (1.0)
* Version 1.0 (Rev. 3)
* General: added asynchronous user parameter and clock
SC EXIT (1.0)
* Version 1.0 (Rev. 8)
* No changes
SC MMU (1.0)
* Version 1.0 (Rev. 7)
* No changes
SC SI_CONVERTER (1.0)
* Version 1.0 (Rev. 8)
* Bug Fix: Prevents over-reading when sub-sized (narrow) single-beat transactions get downsized.
SC SPLITTER (1.0)
* Version 1.0 (Rev. 4)
* No changes
SC TRANSACTION_REGULATOR (1.0)
* Version 1.0 (Rev. 8)
* No changes
SDI RX to Video Bridge (2.0)
* Version 2.0
* No changes
SMPTE SD/HD/3G-SDI (3.0)
* Version 3.0 (Rev. 8)
* No changes
SMPTE UHD-SDI (1.0)
* Version 1.0 (Rev. 7)
* General: UltraScale+ moved to production status
SMPTE UHD-SDI RX (1.0)
* Version 1.0
* No changes
SMPTE UHD-SDI RX SUBSYSTEM (2.0)
* Version 2.0 (Rev. 3)
* Bug Fix: Made GT clock changes and GT hierarchy was updated
* Bug Fix: Updated UHDSDI-GT GUI for reference clock selection
* Bug Fix: added gen_no_clkdiv_12g Rx clock selection for Timing Analysis
* Bug Fix: cleaned CDC violations in KCU116 Example Design
* Revision change in one or more subcores
SMPTE UHD-SDI TX (1.0)
* Version 1.0
* No changes
SMPTE UHD-SDI TX SUBSYSTEM (2.0)
* Version 2.0 (Rev. 3)
* Bug Fix: Updated UHDSDI-GT GUI for GT reference clock selection
* Bug Fix: CDC Warnings are fixed
* Revision change in one or more subcores
SPDIF/AES3 (2.0)
* Version 2.0 (Rev. 21)
* Bug Fix: Status register updates when sample rate changes
* Other: Updates to reset logic to handle CDC
* Other: Added Versal support
* Revision change in one or more subcores
SelectIO Interface Wizard (5.1)
* Version 5.1 (Rev. 13)
* General: Properly tied off the undriven input ports
Sensor Demosaic (1.0)
* Version 1.0 (Rev. 5)
* General: Added Versal support.
* Revision change in one or more subcores
Serial RapidIO Gen2 (4.1)
* Version 4.1 (Rev. 6)
* Revision change in one or more subcores
Shell Card Management Controller Subsystem (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
Shell Card Management Peripheral Subsystem (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
Shell Utility MSP432 BSL CRC Generator (1.0)
* Version 1.0
* No changes
Slice (1.0)
* Version 1.0 (Rev. 2)
* Add bd/bd.tcl to provide get_display_strings.
SmartConnect AXI2SC Bridge (1.0)
* Version 1.0 (Rev. 7)
* No changes
SmartConnect Node (1.0)
* Version 1.0 (Rev. 10)
* No changes
SmartConnect SC2AXI Bridge (1.0)
* Version 1.0 (Rev. 7)
* No changes
SmartConnect Switchboard (1.0)
* Version 1.0 (Rev. 6)
* No changes
Soft ECC Proxy (1.0)
* Version 1.0
* Initial core release
Soft Error Mitigation (4.1)
* Version 4.1 (Rev. 12)
* General: Add support for new 7 Series FPGA.
* General: Update IP packaging to exclude new UltraScale and ACAP devices - no impact to IP functionality.
Soft-Decision FEC (1.1)
* Version 1.1 (Rev. 3)
* Bug Fix: Addressing memory leak in MEX wrapper.
* Bug Fix: Fixed C model crash when multiple DSP IP C models are run together: See (Xilinx Answer 71876)
* Other: Reduce programmable logic clock frequency in example design when -1L parts are specified.
* Other: Correction to transaction file generation on Windows.
* Other: Add DOCSIS ranging codes.
* Revision change in one or more subcores
Stream Traffic Manager (1.0)
* Version 1.0
* No changes
Switch Core Top (1.0)
* Version 1.0 (Rev. 7)
* Revision change in one or more subcores
System Cache (4.0)
* Version 4.0 (Rev. 6)
* General: Added DRC to check cache line length with ACE master coherency
* General: Supported devices and production status are now determined automatically, to simplify support for future devices
System ILA (1.1)
* Version 1.1 (Rev. 5)
* General: Added support for automotive Kintex device
* Revision change in one or more subcores
System Management Wizard (1.3)
* Version 1.3 (Rev. 10)
* General: Internal testbench updates. No affect to the customers.
TMR Comparator (1.0)
* Version 1.0 (Rev. 2)
* No changes
TMR Inject (1.0)
* Version 1.0 (Rev. 3)
* No changes
TMR Manager (1.0)
* Version 1.0 (Rev. 4)
* No changes
TMR Soft Error Mitigation Interface (1.0)
* Version 1.0 (Rev. 8)
* General: Updated supported families.
* Revision change in one or more subcores
TMR Voter (1.0)
* Version 1.0 (Rev. 2)
* No changes
TSN Endpoint Block (1.0)
* Version 1.0 (Rev. 4)
* Revision change in one or more subcores
TSN Tri Mode Ethernet MAC (1.0)
* Version 1.0 (Rev. 4)
* Revision change in one or more subcores
Time-Aware DMA (1.0)
* Version 1.0 (Rev. 3)
* Revision change in one or more subcores
Timer Sync 1588 (1.2)
* Version 1.2 (Rev. 4)
* No changes
Tri Mode Ethernet MAC (9.0)
* Version 9.0 (Rev. 14)
* Bug Fix: Fixed bug which resulted in TX PTP packet buffer contents getting corrupted after user writes to it.
* Bug Fix: Updated Internal mode block-level XDC: Removed set_max_delay constraints for TX-RX timing paths when the IP is generated with clock source set to user_clk2.
* Revision change in one or more subcores
UHD-SDI Audio (2.0)
* Version 2.0 (Rev. 1)
* General: Resolved critical warnings in report methodology stage
UHD-SDI GT (2.0)
* Version 2.0
* Bug Fix: Fixed RTL selection of GT Reference Clocks for RX only configurations
* New Feature: Simplified the GUI options
* New Feature: Enabled HIP flow to use latest files from GT wizard
* Revision change in one or more subcores
UHD-SDI Video Pattern Generator (1.0)
* Version 1.0 (Rev. 1)
* No changes
UltraScale 100G Ethernet Subsystem (2.5)
* Version 2.5
* Port Change: Added additional anlt ability ctl/stat ports
* Bug Fix: Exposed ctl_tx_send_idle, ctl_tx_send_lfi, ctl_tx_send_rfi ports even with AXI4-lite enabled
* Bug Fix: Updated regular expression for devices check
* Bug Fix: Updated TX_DIFFCTRL values in the trans debug module
* Feature Enhancement: Added board tab support for VCU108 board
* Feature Enhancement: Added AXI Streaming User Interface support
* Feature Enhancement: Added AXI4 lite statistics register enablement/disablement in the GUI
* Revision change in one or more subcores
UltraScale FPGA Gen3 Integrated Block for PCI Express (4.4)
* Version 4.4 (Rev. 5)
* Feature Enhancement: Added GUI option to disable the GT channel LOC constraints in GT Wizard IP XDC
* Revision change in one or more subcores
UltraScale FPGAs Transceivers Wizard (1.7)
* Version 1.7 (Rev. 6)
* General: Updated the transceiver configuration preset options for CPRI to cover additional usecases
* Revision change in one or more subcores
UltraScale Soft Error Mitigation (3.1)
* Version 3.1 (Rev. 11)
* General: Added support for additional UltraScale+ devices
* General: Enabled drop-down option to select ICAP and FRAME_ECC hierarchy in Vivado IP Integrator GUI when targeting UltraScale+ devices
UltraScale+ 100G Ethernet Subsystem (2.6)
* Version 2.6
* Port Change: Added additional anlt ability ctl/stat ports
* Bug Fix: Exposed ctl_tx_send_idle, ctl_tx_send_lfi, ctl_tx_send_rfi ports even with AXI4-lite enabled
* Bug Fix: Updated regular expression for devices check
* Bug Fix: Updated TX_DIFFCTRL values in the trans debug module
* Feature Enhancement: Added CAUI4 - GTM_NRZ configuration support
* Feature Enhancement: Added AXI Streaming User Interface support
* Feature Enhancement: Added AXI4 lite statistics register enablement/disablement in the GUI
* Other: Added new UltraScale+ devices support
* Revision change in one or more subcores
UltraScale+ PCI Express 4c Integrated Block (1.0)
* Version 1.0 (Rev. 5)
* Bug Fix: Disabled subsystem vendor ID change for non PF0 case
* Bug Fix: Removed 0 VFs option per PF when SRIOV is enabled. Each enabled PF should have minimum 4VFs when SRIOV is enabled.
* Feature Enhancement: Added GUI option to disable the GT channel LOC constraints in GT Wizard IP XDC
* Feature Enhancement: Added GUI option to change message routing parameter -AXISTEN_IF_ENABLE_MSG_ROUTE
* Revision change in one or more subcores
UltraScale+ PCI Express Integrated Block (1.3)
* Version 1.3 (Rev. 5)
* Bug Fix: Disabled subsystem vendor ID change for non PF0 case
* Bug Fix: Removed 0 VFs option per PF when SRIOV is enabled. Each enabled PF should have minimum 4VFs when SRIOV is enabled.
* Feature Enhancement: Added GUI option to disable the GT channel LOC constraints in GT Wizard IP XDC
* Feature Enhancement: Added GUI option to change message routing parameter-AXISTEN_IF_ENABLE_MSG_ROUTE
* Revision change in one or more subcores
Universal Serial XGMII Ethernet Subsystem (1.1)
* Version 1.1
* Feature Enhancement: Added feature enabling AXI4 statistics counter
* Revision change in one or more subcores
Utility Reduced Logic (2.0)
* Version 2.0 (Rev. 4)
* No changes
Utility Vector Logic (2.0)
* Version 2.0 (Rev. 1)
* No changes
VIO (Virtual Input/Output) (3.0)
* Version 3.0 (Rev. 20)
* General: Internal device support method change
Versal PCI Express Integrated Block (1.0)
* Version 1.0
* Initial release
Versal PCIe PHY IP (1.0)
* Version 1.0
* Initial release
Video AXI4S Remapper (1.0)
* Version 1.0 (Rev. 11)
* Revision change in one or more subcores
Video Color Space Conversion and Correction (1.0)
* Version 1.0 (Rev. 13)
* General: Added Versal support.
* Revision change in one or more subcores
Video Deinterlacer (5.0)
* Version 5.0 (Rev. 13)
* Revision change in one or more subcores
Video DisplayPort 1.4 RX Subsystem (2.1)
* Version 2.1
* Bug Fix: XDCB-5 warnings fixed in XDC constraints
* Bug Fix: AXI-4 lite register 0x7F0 is mirrored to 0x02201 DPCD register for MAX_LINE_RATE. This will enable to limit the DP 1.4 Subsystem line rate to 5.4 Gbps
* Bug Fix: TP1 reset pulse width is increased to make it detect in drp_clk of vid_phy controller
* Bug Fix: Updated the 0x0A and 0x0B DPCD registers when Audio is enabled
* Bug Fix: Interrupt module is updated to mask the no_video interrupt on streams 2,3,4 when SST is mode is selected through software in the MST capable system
* Bug Fix: Added ALMOST FULL pin to HDCP Egress and Ingress FIFOs. It is used to avoid data corruption when HDCP is enabled
* New Feature: Added MST FB Pass-through example design
* Feature Enhancement: Added Audio Clock Regeneration Interface
* Feature Enhancement: KCU105 pass-through example timing closure for 8.1 Gbps
* Feature Enhancement: VCU118 RX-only example design baud rate is updated to 115200 inline with other example design
* Feature Enhancement: Added YUV4422 and YUV444 support in ZCU102 pass-Through example design and removed ACR interface since it was not used
* Revision change in one or more subcores
Video DisplayPort 1.4 TX Subsystem (2.1)
* Version 2.1
* Bug Fix: XDCB-5 warnings fixed in XDC constraints
* Bug Fix: M-VID and N-VID values are updated in asynchronous mode on AXI-4 Lite 0x1AC and 0x1B4 registers respectively
* Bug Fix: Added ALMOST FULL pin to HDCP Egress and Ingress FIFOs. It is used to avoid data corruption when HDCP is enabled
* New Feature: Added MST FB Pass-through example design
* Feature Enhancement: KCU105 pass-through example timing closure for 8.1 Gbps
* Feature Enhancement: VCU118 TX-only example design baud rate is updated to 115200 inline with other example design
* Revision change in one or more subcores
Video Frame Buffer Read (2.1)
* Version 2.1 (Rev. 2)
* General: Added 12 and 16 bpc support.
* General: Added Versal support
* Revision change in one or more subcores
Video Frame Buffer Write (2.1)
* Version 2.1 (Rev. 2)
* General: Added 12 and 16 bpc support.
* General: Added Versal support
* Revision change in one or more subcores
Video Horizontal Chroma Resampler (1.0)
* Version 1.0 (Rev. 13)
* Revision change in one or more subcores
Video Horizontal Scaler (1.0)
* Version 1.0 (Rev. 13)
* Revision change in one or more subcores
Video In to AXI4-Stream (4.0)
* Version 4.0 (Rev. 9)
* No changes
Video Letterbox Engine (1.0)
* Version 1.0 (Rev. 13)
* Revision change in one or more subcores
Video Mixer (4.0)
* Version 4.0
* Feature Enhancement: Increased number of overlay layers from 8 to 16
* Other: Logo layer enable bit updated from bit 15 to bit 23
* Other: Added Versal support
* Revision change in one or more subcores
Video Multi-Scaler (1.0)
* Version 1.0 (Rev. 1)
* General: Added Versal support
* Revision change in one or more subcores
Video On Screen Display (6.0)
* Version 6.0 (Rev. 16)
* No changes
Video PHY Controller (2.2)
* Version 2.2 (Rev. 3)
* Bug Fix: Removed the IBUFDS input in constraints in main XDC to solve Critical Warning.
* Bug Fix: Updated gthe3_common_wrapper to correct FBDIV to 40
* Bug Fix: Added CPLL Railing module in DP 7 Series to solve intermittent CPLL hanging issue
* Other: Changed all supported UltraScale+ devices to Production
* Other: Supports HDMI 1.4/2.0 and Display Port Subsystems only
* Other: Supports 7 Series, UltraScale and UltraScale+ devices only
* Other: HDMI support for GTPE2, GTXE2, GTHE3, GTHE4 and GTYE4 transceivers only
* Other: DisplayPort support for GTXE2, GTHE3, GTHE4 and GTYE4 transceivers only
* Revision change in one or more subcores
Video Processing Subsystem (2.1)
* Version 2.1
* General: Added 64 bit configuration option in GUI for deinterlacer
* General: BUG Fixes for 8k resolution
* General: Added Versal support
* Revision change in one or more subcores
Video Scene Change Detection (1.0)
* Version 1.0 (Rev. 1)
* General: Verified 64-bit addressing
* General: Added Versal support
* Revision change in one or more subcores
Video Test Pattern Generator (8.0)
* Version 8.0 (Rev. 1)
* General: Added motion enable for color bar pattern.
* General: Added Versal support.
* Revision change in one or more subcores
Video Timing Controller (6.1)
* Version 6.1 (Rev. 13)
* No changes
Video Vertical Chroma Resampler (1.0)
* Version 1.0 (Rev. 13)
* Revision change in one or more subcores
Video Vertical Scaler (1.0)
* Version 1.0 (Rev. 13)
* Revision change in one or more subcores
Video to SDI TX Bridge (2.0)
* Version 2.0
* No changes
Virtex UltraScale+ FPGAs GTM Transceivers Wizard (1.0)
* Version 1.0 (Rev. 1)
* Feature Enhancement: Added support to have two instances of 50G FEC transcoding blocks
* Feature Enhancement: Adjusted line rate range supported to match the UltraScale+ FPGAs Data Sheet
* Feature Enhancement: Added support to for independent FEC configuration selection in a dual
* Feature Enhancement: SIM_RESET_SPEEDUP attribute added to GTM_DUAL UNISIM primitive
* Feature Enhancement: Updated reset controller helper block
* Feature Enhancement: Updated example design XDC MAX_PROG_DELAY values to 0
* Revision change in one or more subcores
Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.3)
* Version 4.3 (Rev. 4)* No changes
Viterbi Decoder (9.1)
* Version 9.1 (Rev. 11)
* Revision change in one or more subcores
XADC Wizard (3.3)
* Version 3.3 (Rev. 6)
* No changes
XAUI (12.3)
* Version 12.3 (Rev. 6)
* General: Support for zqzu29dr devices
* General: This IP will be deprecated from 2019.2 release onwards. Please contact your Xilinx FAE if you are looking for this IP.
* Revision change in one or more subcores
XHMC (1.0)
* Version 1.0 (Rev. 9)
* Bug Fix: For UltraScale+ devices, limiting the 15G link speed for -2, -3, -2L speed grades; for -1LV speed grade link speed is limited to 10G
* Revision change in one or more subcores
YCrCb to RGB Color-Space Converter (7.1)
* Version 7.1 (Rev. 13)
* No changes
ZYNQ UltraScale+ SYNC IP V1_0 (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
ZYNQ UltraScale+ VCU (1.2)
* Version 1.2 (Rev. 1)
* Port Change: NONE
* Bug Fix: NONE
* Feature Enhancement: NONE
* Other: NONE
* Other: version 1.2
ZYNQ UltraScale+ VCU DDR4 Controller (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
ZYNQ7 Processing System (5.5)
* Version 5.5 (Rev. 6)
* No changes
ZYNQ7 Processing System VIP (1.0)
* Version 1.0 (Rev. 7)
* Revision change in one or more subcores
ZYNQMPSOC Processing System VIP (1.0)
* Version 1.0 (Rev. 5)
* Revision change in one or more subcores
Zynq UltraScale+ MPSoC (3.3)
* Version 3.3
* Bug Fix: 1.Fix for DMA based peripherals to work with SMMU.
* Bug Fix: 2.Updated the ddrc, phy driver files to set LPDDR4 VREF CA value to "30.8 %"
* Bug Fix: 3.clk_to_pl_bufg port is disabled when internal clock source is used for gem TSU clock
* Feature Enhancement: 1.Support added for Dynamic DDR controller configuration.
* Feature Enhancement: 2.Support added for GPIO polarity control.
* Feature Enhancement: 3.Added Manual QoS setting support for HP interface.
* Feature Enhancement: 4.Added USB3 dual clock enablement support.
* Revision change in one or more subcores
Zynq UltraScale+ RF Data Converter (2.1)
* Version 2.1 (Rev. 2)
* Bug Fix: Fixed the demonstration testbench data checker for DAC Nyquist zone 2
* Bug Fix: Fixed the demonstration testbench data checkers for DAC and ADC inverted Q output
* Bug Fix: Fixed issue where GUI would allow reference clock frequencies above the maximum supported by the PLL
* Bug Fix: Fixed rounding issue for the data stimulus block clock in the IP Integrator example design
* New Feature: Added support for RF Analyzer
* New Feature: Added background calibration bypass option
* New Feature: Added an interrupt for when the POR Finite State Machine detects an error in the power-up sequence
* Other: Added parameter for total number of slices per Tile
* Other: Changed Mixer Type to "Off" for ADC slices 1 and 3 when in Bypass IQ->IQ mode
* Other: Removed the "_i" extension from the component name in the IP Integrator example design
* Other: Removed the following parameters which were not used by the IP DAC_AdderXY_Enable, DAC_FifoXY_Enable, DAC1_Output_Current and DAC2_Output_Current, ADC_FifoXY_Enable
* Other: Removed ADC/DAC debug options from IP GUI
* Other: Removed calibration time option from GUI
* Other: Removed pblock constraints from example design
* Other: Reduced maximum ADC sample rate for gen 2 devices
audio_tpg_v1_0 (1.0)
* Version 1.0
* No changes
axi_msg (1.0)
* Version 1.0 (Rev. 5)
* Revision change in one or more subcores
axi_sg (4.1)
* Version 4.1 (Rev. 12)
* Revision change in one or more subcores
gtm_cntrl (1.0)
* Version 1.0 (Rev. 1)
* Feature Enhancement: BRAM INIT strings update
* Revision change in one or more subcores
interrupt_controller (3.1)
* Version 3.1 (Rev. 4)
* No changes
lib_bmg (1.0)
* Version 1.0 (Rev. 12)
* xpm memory read latency and initialization parameters added
* Revision change in one or more subcores
lib_cdc (1.0)
* Version 1.0 (Rev. 2)
* No changes
lib_fifo (1.0)
* Version 1.0 (Rev. 13)
* XPM use by default
* Revision change in one or more subcores
lib_pkg (1.0)
* Version 1.0 (Rev. 2)
* No changes
lib_srl_fifo (1.0)
* Version 1.0 (Rev. 2)
* No changes
| AR# 72242 | |
|---|---|
| 日期 | 05/29/2019 |
| 状态 | Active |
| Type | 版本说明 |
| Tools | |