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100G Multirate Ethernet MAC (MRMAC) (1.3)
* Version 1.3
* Feature Enhancement: Updates in Reference design for 10G/25GE with 1588 for driver testing and beta customer access
* Feature Enhancement: Versal GT reset helper ports changed.
* Feature Enhancement: PTP System Timer moved to example design.
* Feature Enhancement: Example design update and timing improvements.
* Feature Enhancement: One or more port changes in IP
* Feature Enhancement: New Presets added in GUI
* Feature Enhancement: MRMAC IP Pre-Production now
* Revision change in one or more subcores
100M/1G TSN Subsystem (2.0)
* Version 2.0 (Rev. 6)
* General: Updated with waivers in the XDC
* Revision change in one or more subcores
10G Ethernet MAC (15.1)
* Version 15.1 (Rev. 9)
* General: Updated to support production silicon for Spartan-7 and ASpartan-7 devices
10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)
* Version 6.0 (Rev. 18)
* Revision change in one or more subcores
10G Ethernet Subsystem (3.1)
* Version 3.1 (Rev. 14)
* Revision change in one or more subcores
10G/25G Ethernet Subsystem (3.3)
* Version 3.3
* Feature Enhancement: Timer syncer module will be always present in the example design, out-side the IP
* Feature Enhancement: Removed the timer syncer IP present inside CORE for the 32-bit variant core configuration with Enable Timestamping Logic feature
* Other: New device support added
* Other: gt_reset_ip version update
* Other: dclk_0 and sys_reset_0 port added for CMAC RSFEC
* Revision change in one or more subcores
1G/10G/25G Switching Ethernet Subsystem (2.6)
* Version 2.6
* Port Change: Added new port rxrecclkout for all core configuration
* Bug Fix: Updated for TIMING DRCs
* Feature Enhancement: Added 802.1cm preemption feature for 64-bit variant
* Feature Enhancement: Added RS-FEC optionally for 64-bit variant
* Feature Enhancement: Versal support added
* Other: New device support added
* Other: Updated the freq_hz param to integer type for dclk port for IPI
* Revision change in one or more subcores
1G/2.5G Ethernet PCS/PMA or SGMII (16.2)
* Version 16.2 (Rev. 1)
* Bug Fix: Fixed the GUI issue while selecting the 1000BaseX over LVDS the LVDS refclk option should not be visible
* Bug Fix: Fixed the BOTH configuration option visibility based on the GT availability
* Other: Updated the freq_hz parameter to integer for independent_clock_bufg port
* Other: Updated with syncers as a part of IP waivers at Axi Ethernet HIP
* Other: Updated the gt_quad_base and gt_reset_ip core version to v1.1
* Revision change in one or more subcores
32-bit Initiator/Target for PCI (7 Series) (5.0)
* Version 5.0 (Rev. 12)
* No changes
3GPP LTE Channel Estimator (2.0)
* Version 2.0 (Rev. 17)
* No changes
3GPP LTE MIMO Decoder (3.0)
* Version 3.0 (Rev. 16)
* No changes
3GPP LTE MIMO Encoder (4.0)
* Version 4.0 (Rev. 15)
* No changes
3GPP Mixed Mode Turbo Decoder (2.0)
* Version 2.0 (Rev. 20)
* No changes
3GPP Turbo Encoder (5.0)
* Version 5.0 (Rev. 16)
* No changes
3GPPLTE Turbo Encoder (4.0)
* Version 4.0 (Rev. 16)
* No changes
40G/50G Ethernet Subsystem (3.2)
* Version 3.2
* General: new device support added
* General: gt_reset_ip version update
* Revision change in one or more subcores
64-bit Initiator/Target for PCI (7-Series) (5.0)
* Version 5.0 (Rev. 11)
* No changes
7 Series FPGAs Transceivers Wizard (3.6)
* Version 3.6 (Rev. 13)
* General: VbyOne preset is added
7 Series Integrated Block for PCI Express (3.3)
* Version 3.3 (Rev. 14)
* General: Added Zynq 7z030i,7z035i,7z045i and 7z100i device support
ADC DAC Interface IP (1.0)
* Version 1.0
* Initial Release
* Interface speed support from 400Mbps - 1332Mbps for 1LP, 1LHP, 1MP -- 400Mbps - 1468Mbps for 2MP -- 400Mbps - 1600Mbps for 2HP, 3HP
* Added Interface Mode support for SDR
* Supported Data Bus Directions include RX_ONLY TX_ONLY TX+RX
* Supported Data Bus I/O Types are both Single_Ended and Differential
* Drop down selection for IOSTANDARDS
* REFCLK_TYPE supported options are Bit_Clock and Frame_Clock
* REFCLK_DIVIDE -- List of divide options in dropdown, supported for REFCLK_TYPE=Frame_Clock
* Application Datawidth -- 12, 14, 16
* TX_NUM_PINS/RX_NUM_PINS -- Support of Maximum of 3 I/O banks (162 I/O pins)
AHB-Lite to AXI Bridge (3.0)
* Version 3.0 (Rev. 17)
* Revision change in one or more subcores
AI Engine (2.0)
* Version 2.0
* Feature Enhancement: Initial public release
* Feature Enhancement: Changed default value according to requirement for building the custom platform
* Feature Enhancement: Removed most of the parameters from the GUI as interface ports are configured and connected using the Vitis linker
* Feature Enhancement: Revision change in one or more subcores
* Revision change in one or more subcores
AMM Master Bridge (1.0)
* Version 1.0 (Rev. 8)
* General: Updated Avalon Interface ADDR_WIDTH parameter. No functional changes
* Revision change in one or more subcores
AMM Slave Bridge (1.0)
* Version 1.0 (Rev. 12)
* Revision change in one or more subcores
AXI 1G/2.5G Ethernet Subsystem (7.2)
* Version 7.2 (Rev. 1)
* General: Updated with waivers in the XDC
* General: Refer to tri_mode_ethernet_mac v9_0 and gig_ethernet_pcs_pma v16_2 core change logs for changes in the sub cores of this core
* General: Updated the gt_quad_base and gt_reset_ip to version 1.1
* Revision change in one or more subcores
AXI AHB Lite Bridge (3.0)
* Version 3.0 (Rev. 19)
* Revision change in one or more subcores
AXI APB Bridge (3.0)
* Version 3.0 (Rev. 17)
* General: IPI related errors have been downgraded to warnings
AXI BRAM Controller (4.1)
* Version 4.1 (Rev. 4)
* General: Vivado Block Design warnings on READ_LATENCY and RD_CMD_OPT parameters fixed. No functional change.
AXI Bridge for PCI Express Gen3 Subsystem (3.0)
* Version 3.0 (Rev. 13)
* General: Added civ devices vu440_civ,ku115_civ. -
* Revision change in one or more subcores
AXI CAN (5.0)
* Version 5.0 (Rev. 25)
* Revision change in one or more subcores
AXI Central Direct Memory Access (4.1)
* Version 4.1 (Rev. 22)
* General: Updated the tool tip for DRE checkbox
* General: Fixed the race condition that can occur when programming tail descriptor for address width greater than 32
* Revision change in one or more subcores
AXI Chip2Chip Bridge (5.0)
* Version 5.0 (Rev. 9)
* General: Chip2Chip Versal Block Automation Updated.
* Revision change in one or more subcores
AXI Clock Converter (2.1)
* Version 2.1 (Rev. 21)
* Revision change in one or more subcores
AXI Crossbar (2.1)
* Version 2.1 (Rev. 23)
* Revision change in one or more subcores
AXI Data FIFO (2.1)
* Version 2.1 (Rev. 21)
* Revision change in one or more subcores
AXI Data Width Converter (2.1)
* Version 2.1 (Rev. 22)
* Revision change in one or more subcores
AXI DataMover (5.1)
* Version 5.1 (Rev. 24)
* Revision change in one or more subcores
AXI Direct Memory Access (7.1)
* Version 7.1 (Rev. 23)
* Revision change in one or more subcores
AXI EMC (3.0)
* Version 3.0 (Rev. 22)
* General: Updates to example design. No functional changes
* Revision change in one or more subcores
AXI EPC (2.0)
* Version 2.0 (Rev. 25)
* Revision change in one or more subcores
AXI Ethernet Buffer (2.0)
* Version 2.0 (Rev. 23)
* Bug Fix: Fixed the XPM memory collision issue handling in some scenarios for the 2.5G line rate
* Other: Updated with waivers in the XDC
AXI Ethernet Clocking (2.0)
* Version 2.0 (Rev. 2)
* No changes
AXI EthernetLite (3.0)
* Version 3.0 (Rev. 21)
* General: Updated the IP waiver format in the XDC
* General: Applied keep true attribute for the phy_col port as synthesis tool optimized for Duplex mode
* Revision change in one or more subcores
AXI GPIO (2.0)
* Version 2.0 (Rev. 24)
* General: No Functional changes
* Revision change in one or more subcores
AXI HB ICAP (1.0)
* Version 1.0 (Rev. 3)
* General: No functional change
AXI HWICAP (3.0)
* Version 3.0 (Rev. 26)
* General: minor RTL updates. No Functional changes
* Revision change in one or more subcores
AXI IIC (2.0)
* Version 2.0 (Rev. 25)
* Revision change in one or more subcores
AXI Interconnect (2.1)
* Version 2.1 (Rev. 23)
* Revision change in one or more subcores
AXI Interrupt Controller (4.1)
* Version 4.1 (Rev. 15)
* General: Consider interrupts and processor clock asynchronous if they have different clock drivers than the AXI clock.
AXI Lite IPIF (3.0)
* Version 3.0 (Rev. 4)
* No changes
AXI MMU (2.1)
* Version 2.1 (Rev. 20)
* Revision change in one or more subcores
AXI Master Burst (2.0)
* Version 2.0 (Rev. 7)
* No changes
AXI Memory Init (1.0)
* Version 1.0 (Rev. 3)
* Revision change in one or more subcores
AXI Memory Mapped To PCI Express (2.9)
* Version 2.9 (Rev. 4)
* Feature Enhancement: Added support for device xa7k160t
* Feature Enhancement: Support of CPG236/CPG238 re-established for x2 modes
* Revision change in one or more subcores
AXI Memory Mapped to Stream Mapper (1.1)
* Version 1.1 (Rev. 21)
* Revision change in one or more subcores
AXI Multi Channel Direct Memory Access (1.1)
* Version 1.1 (Rev. 3)
* Revision change in one or more subcores
AXI Performance Monitor (5.0)
* Version 5.0 (Rev. 24)
* Revision change in one or more subcores
AXI Protocol Checker (2.0)
* Version 2.0 (Rev. 8)
* Revision change in one or more subcores
AXI Protocol Converter (2.1)
* Version 2.1 (Rev. 22)
* Revision change in one or more subcores
AXI Protocol Firewall (1.1)
* Version 1.1 (Rev. 1)
* General: Example design support for Versal parts
* Revision change in one or more subcores
AXI Quad SPI (3.2)
* Version 3.2 (Rev. 21)
* General: Versal Support and Constraints cleanup.
* Revision change in one or more subcores
AXI Register Slice (2.1)
* Version 2.1 (Rev. 22)
* Revision change in one or more subcores
AXI Remapper IP for Rx (1.0)
* Version 1.0
* Initial Vivado Release
AXI Remapper IP for Tx (1.0)
* Version 1.0
* Initial Vivado Release
AXI Sideband Utility (1.0)
* Version 1.0 (Rev. 6)
* Revision change in one or more subcores
AXI SmartConnect (1.0)
* Version 1.0 (Rev. 14)
* Feature Enhancement: Add priority arbitration option
* Revision change in one or more subcores
AXI TFT Controller (2.0)
* Version 2.0 (Rev. 23)
* No changes
AXI Timebase Watchdog Timer (3.0)
* Version 3.0 (Rev. 14)
* Revision change in one or more subcores
AXI Timer (2.0)
* Version 2.0 (Rev. 24)
* Revision change in one or more subcores
AXI Traffic Generator (3.0)
* Version 3.0 (Rev. 8)
* General: no functional changes
* General: Updated the vivado_user_config.sv file for High level traffic with traffic profile Ethernet mode.
* Revision change in one or more subcores
AXI UART16550 (2.0)
* Version 2.0 (Rev. 24)
* General: update in coreinfo.yml.
* Revision change in one or more subcores
AXI USB2 Device (5.0)
* Version 5.0 (Rev. 23)
* Revision change in one or more subcores
AXI Uartlite (2.0)
* Version 2.0 (Rev. 26)
* Revision change in one or more subcores
AXI Verification IP (1.1)
* Version 1.1 (Rev. 8)
* General: added new feature
* Revision change in one or more subcores
AXI Video Direct Memory Access (6.3)
* Version 6.3 (Rev. 10)
* General: No functional change.
* Revision change in one or more subcores
AXI Virtual FIFO Controller (2.0)
* Version 2.0 (Rev. 24)
* Revision change in one or more subcores
AXI-Stream FIFO (4.2)
* Version 4.2 (Rev. 4)
* Revision change in one or more subcores
AXI4 Debug Hub (2.0)
* Version 2.0
* General: Added Narrow burst
AXI4-Stream Accelerator Adapter (2.1)
* Version 2.1 (Rev. 16)
* No changes
AXI4-Stream Broadcaster (1.1)
* Version 1.1 (Rev. 21)
* General: support for auto constraint generation
* Revision change in one or more subcores
AXI4-Stream Clock Converter (1.1)
* Version 1.1 (Rev. 23)
* Revision change in one or more subcores
AXI4-Stream Combiner (1.1)
* Version 1.1 (Rev. 20)
* Revision change in one or more subcores
AXI4-Stream Data FIFO (2.0)
* Version 2.0 (Rev. 4)
* Revision change in one or more subcores
AXI4-Stream Data Width Converter (1.1)
* Version 1.1 (Rev. 21)
* Revision change in one or more subcores
AXI4-Stream Interconnect (2.1)
* Version 2.1 (Rev. 23)
* Revision change in one or more subcores
AXI4-Stream Protocol Checker (2.0)
* Version 2.0 (Rev. 6)
* Revision change in one or more subcores
AXI4-Stream Register Slice (1.1)
* Version 1.1 (Rev. 22)
* General: Fix SLR TDM Crossing mode (type 13) to utilize SLL Regs (Laguna sites).
* Revision change in one or more subcores
AXI4-Stream Subset Converter (1.1)
* Version 1.1 (Rev. 22)
* General: support auto constraint generation
* Revision change in one or more subcores
AXI4-Stream Switch (1.1)
* Version 1.1 (Rev. 22)
* Revision change in one or more subcores
AXI4-Stream Verification IP (1.1)
* Version 1.1 (Rev. 8)
* Revision change in one or more subcores
AXI4-Stream to Video Out (4.0)
* Version 4.0 (Rev. 11)
* Bug Fix: Added SoF state signal for Asynchronous for HDMI/DP protocols
Accumulator (12.0)
* Version 12.0 (Rev. 14)
* No changes
Adder/Subtracter (12.0)
* Version 12.0 (Rev. 14)
* No changes
Advanced Encryption Standard (AES) (1.1)
* Version 1.1 (Rev. 2)
* General: Removed all the Seven Series Device Support
Advanced IO Wizard (1.0)
* Version 1.0 (Rev. 3)
* Feature Enhancement: BIDIR Support
* Revision change in one or more subcores
Audio Clock Recovery Unit (1.0)
* Version 1.0 (Rev. 2)
* General: Uniquification update
Audio Formatter (1.0)
* Version 1.0 (Rev. 4)
* Revision change in one or more subcores
Aurora 64B66B (12.0)
* Version 12.0 (Rev. 3)
* General: Aurora block automation updated for Versal
* General: RPLL support added for Versal
* Revision change in one or more subcores
Aurora 8B10B (11.1)
* Version 11.1 (Rev. 10)
* General: Support removed for Zynq UltraScale+ (xck26) devices
* Revision change in one or more subcores
Auto-negotiation and Link Training (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
BUFG GT (1.0)
* Version 1.0 (Rev. 3)
* General: CLK DOMAIN and PHASE properties added to the pins usrclk and outclk
Binary Counter (12.0)
* Version 12.0 (Rev. 14)
* No changes
Block Memory Generator (8.4)
* Version 8.4 (Rev. 4)
* No changes
CANFD (3.0)
* Version 3.0 (Rev. 1)
* Revision change in one or more subcores
CIC Compiler (4.0)
* Version 4.0 (Rev. 15)
* No changes
CORDIC (6.0)
* Version 6.0 (Rev. 16)
* No changes
CPRI (8.11)
* Version 8.11 (Rev. 5)
* Port Change: Added ch_txmstdatapathreset & ch_rxmstdatapathreset output ports to Versal GT interfaces to support gt_reset_ip_v1.1.
* Bug Fix: Fixed a bug in HFNSYNC module where there was a remote chance of the core failing to align to the received hyperframe correctly.
* Bug Fix: Fixed a bug in Versal designs where Block Automation would not run on more than one CPRI core.
* Bug Fix: In Versal designs tx/rxmstresetdone and tx/rxpmaresetdone inputs from the GT Quad are now synchronized onto the aux_clk/s_axi_aclk domain.
* Feature Enhancement: Customized Connections option added to Block Automation in Versal designs.
* Feature Enhancement: Removed encommaalign logic from Versal block designs, not required from 2020.2.
* Feature Enhancement: Updated to support version 1.1 of the gt_reset_ip sub-ip core.
* Other: Added Versal GT and Refclk location constraints to the CPRI example design, this removes MGTIO DRC errors.
* Revision change in one or more subcores
Card Management Solution Subsystem (3.0)
* Version 3.0 (Rev. 1)
* Revision change in one or more subcores
Clock Verification IP (1.0)
* Version 1.0 (Rev. 2)
* No changes
Clocking Wizard (1.0)
* Version 1.0 (Rev. 4)
* Feature Enhancement: Added Safe Clock Startup and MBUFGCE Enhancements features
Clocking Wizard (6.0)
* Version 6.0 (Rev. 6)
* Bug Fix: Internal GUI fixes
* Other: CR Fixes
Compact GT (1.0)
* Version 1.0 (Rev. 8)
* Revision change in one or more subcores
Complex Multiplier (6.0)
* Version 6.0 (Rev. 19)
* General: Improved QoR for Versal DSPCPLX cases with full pipelining.
Concat (2.1)
* Version 2.1 (Rev. 4)
* Increased the number of input ports from 32 to 128.
Constant (1.1)
* Version 1.1 (Rev. 7)
* No changes
Control, Interfaces & Processing System (2.1)
* Version 2.1
* Bug Fix: Added missing QDMA H2C descriptor bypass output interface signals
* Bug Fix: XDMA,MULTQ and Bridge Base and High address are set correctly
* Bug Fix: Fixed initial credits assigned to DMA through user controlled parameter
* Bug Fix: Fixed PCIe-MSIX attribute values and XPIPE parameter values
* Feature Enhancement: CPM Port and interface are renamed to improve readability and match port names with Soft DMA IPs
* Feature Enhancement: Enabled User FLR for XDMA mode
* Feature Enhancement: Added Tandem support for CPM
* Feature Enhancement: Improved timing by adding asynchronous clock groups for GT XPIPE clocks
* Feature Enhancement: Added PS9 VIP for simulation
* Feature Enhancement: Added support for Ax Cache to CPM <-> NOC AXI-MM ports in DMA modes
* Feature Enhancement: Added support for Mailbox and 10-bit extended tags in GUI
* Feature Enhancement: Added Lane reversal feature for PCIe controllers 0/1 in GUI
* Feature Enhancement: Added PCIe Link debug feature
* Feature Enhancement: Debug-Hub support is removed from block automation
* Feature Enhancement: Board preset option is removed from block automation and moved to CIPS GUI
* Feature Enhancement: SEM name is changed to XilSEM Library
* Feature Enhancement: VCO output column is removed and Output clock frequency column is added in PLL clocks
* Feature Enhancement: LVCMOS2.5 voltage option is added for MIOs
* Feature Enhancement: HSDP is shown by default which was under param control in 2020.1
* Feature Enhancement: VCC voltage names are updated in Tamper config page.
* Feature Enhancement: References of CPM are replaced with CPM4 in GUI
* Feature Enhancement: Multiple flash support added to select one flash or multiple flashes by selecting Single or Dual Stacked as OSPI Mode.
* Feature Enhancement: Removed IRO/2 from the options of SYSMON clock in PS-PMC tab.
Convolution Encoder (9.0)
* Version 9.0 (Rev. 15)
* No changes
DDR3 SDRAM (MIG) (1.4)
* Version 1.4 (Rev. 10)
* General: Updated for 2020.2
* Revision change in one or more subcores
DDR4 SDRAM (MIG) (2.2)
* Version 2.2 (Rev. 10)
* Feature Enhancement: Ping-Pong PHY UltraScale+ enhancement
* Revision change in one or more subcores
DDS Compiler (6.0)
* Version 6.0 (Rev. 20)
* No changes
DFX AXI Shutdown Manager (1.0)
* Version 1.0
* No changes
DFX Bitstream Monitor (1.0)
* Version 1.0
* No changes
DFX Controller (1.0)
* Version 1.0 (Rev. 1)
* General: Fixes a bug where the lutram ROMs were being optimized away, preventing the core from being programed in the netlist
DFX Decoupler (1.0)
* Version 1.0 (Rev. 1)
* General: Made AXI ACLK and ARESETN compulsory for AXIMM and AXIS interfaces that are being decoupled. These ports only appear on Versal devices. There is no change for non-Versal devices
* General: Changed behavior in IP Integrator to prevent the decoupler being connected between two SmartConnects. This configuration will fail in hardware.
DMA/Bridge Subsystem for PCI Express (4.1)
* Version 4.1 (Rev. 8)
* General: Added XCZU43DR and XCVU57P device support.
* Revision change in one or more subcores
DP DSC AXI4-Stream to Video Out (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
DSP Macro (1.0)
* Version 1.0 (Rev. 1)
* General: Device support expanded.
DSP48 Macro (3.0)
* Version 3.0 (Rev. 18)
* General: This core has been replaced by the DSP Macro v1.0 IP. The DSP48 Macro core will be removed in the 2021.1 Vivado Release and IP instances will automatically upgrade to DSP Macro v1.0.
DUC/DDC Compiler (3.0)
* Version 3.0 (Rev. 15)
* No changes
Debug Bridge (3.0)
* Version 3.0 (Rev. 6)
* No changes
Debug Interface Module (1.0)
* Version 1.0
* No changes
Discrete Fourier Transform (4.2)
* Version 4.2 (Rev. 1)
* Bug Fix: MEX wrapper did not support new point sizes.
DisplayPort (9.0)
* Version 9.0 (Rev. 3)
* Bug Fix: Generate Aux stop/defer for burst aux read transaction
DisplayPort RX Subsystem (2.1)
* Version 2.1 (Rev. 8)
* Bug Fix: Updated lnk_clk constraint precision in XDC
* Revision change in one or more subcores
DisplayPort TX Subsystem (2.1)
* Version 2.1 (Rev. 8)
* Bug Fix: Updated lnk_clk constraint precision in XDC
* Revision change in one or more subcores
Distributed Memory Generator (8.0)
* Version 8.0 (Rev. 13)
* No changes
Divider Generator (5.1)
* Version 5.1 (Rev. 17)
* Revision change in one or more subcores
Double Data Rate Sampling (1.0)
* Version 1.0
* No changes
ECC (2.0)
* Version 2.0 (Rev. 13)
* No changes
ERNIC (3.0)
* Version 3.0
* General: resource optimization and PFC Feature addition
ETRNIC (1.1)
* Version 1.1 (Rev. 3)
* No changes
FEC 5G Common Utilities (1.1)
* Version 1.1 (Rev. 1)
* No changes
FIFO Generator (13.2)
* Version 13.2 (Rev. 5)
* No changes
FIR Compiler (7.2)
* Version 7.2 (Rev. 15)
* Bug Fix: Fixed incorrect application of symmetry when Interpolation_Rate > clk_freq/samp_freq > 1
* Feature Enhancement: Improved GUI error reporting for designs that do not fit within selected device.
* Other: Windows C model compilation now uses Visual Studio 2017
Fast Fourier Transform (9.1)
* Version 9.1 (Rev. 5)
* Revision change in one or more subcores
Fibre Channel 32GFC RS-FEC (1.0)
* Version 1.0 (Rev. 16)
* General: Updated clock wizard parameters in example design.
* Revision change in one or more subcores
Fixed Interval Timer (2.0)
* Version 2.0 (Rev. 10)
* No changes
FlexO 100G RS-FEC (1.0)
* Version 1.0 (Rev. 16)
* General: Updated device support
* Revision change in one or more subcores
Floating-point (7.1)
* Version 7.1 (Rev. 11)
* General: further work-around for inclusion of glbl.sv. No change to functionality.
* General: Windows C model compilation now uses Visual Studio 2017
* General: fix to multiple driver issue on divide_by_zero.
* General: fix for ALUMODE Versal ES1.
G.709 FEC Encoder/Decoder (2.4)
* Version 2.4 (Rev. 2)
* No changes
G.975.1 EFEC I.4 Encoder/Decoder (1.0)
* Version 1.0 (Rev. 18)
* No changes
G.975.1 EFEC I.7 Encoder/Decoder (2.0)
* Version 2.0 (Rev. 18)
* No changes
Gamma LUT (1.1)
* Version 1.1
* General: Added Vitis Support
* Revision change in one or more subcores
GMII to RGMII (4.1)
* Version 4.1
* No changes
HBM IP (1.0)
* Version 1.0 (Rev. 9)
* General: Updated for 2020.2
HDCP (1.0)
* Version 1.0 (Rev. 3)
* No changes
HDCP 2.2 Cipher (1.0)
* Version 1.0 (Rev. 3)
* No changes
HDCP 2.2 Cipher for DP (1.0)
* Version 1.0
* No changes
HDCP 2.2 Montgomery Modular Multiplier (1.0)
* Version 1.0 (Rev. 2)
* No changes
HDCP 2.2 Random Number Generator (1.0)
* Version 1.0 (Rev. 1)
* No changes
HDCP 2.2 Receiver (1.0)
* Version 1.0 (Rev. 14)
* Revision change in one or more subcores
HDCP 2.2 Receiver for DisplayPort 1.4 Subsystems (1.0)
* Version 1.0 (Rev. 3)
* Revision change in one or more subcores
HDCP 2.2 Transmitter (1.0)
* Version 1.0 (Rev. 14)
* Revision change in one or more subcores
HDCP 2.2 Transmitter for DisplayPort 1.4 Subsystem (1.0)
* Version 1.0 (Rev. 3)
* Revision change in one or more subcores
HDMI 1.4/2.0 Receiver (3.0)
* Version 1.1
* No changes
HDMI 1.4/2.0 Receiver Subsystem (3.1)
* Version 3.1 (Rev. 6)
* Bug Fix: Versal Example Designs Critical Warnings are fixed
* New Feature: Added Block Automation Support
* New Feature: HDCP 2.3 Support
* Revision change in one or more subcores
HDMI 1.4/2.0 Transmitter (3.0)
* Version 2.0
* No changes
HDMI 1.4/2.0 Transmitter Subsystem (3.1)
* Version 3.1 (Rev. 6)
* Bug Fix: Versal Example Designs Critical Warnings are fixed
* New Feature: Added Block Automation Support
* New Feature: HDCP 2.3 Support
* Revision change in one or more subcores
HDMI 2.0/2.1 Receiver (1.0)
* Version 1.0
* No changes
HDMI 2.0/2.1 Transmitter (1.0)
* Version 1.0
* No changes
HDMI 2.1 Receiver Subsystem (1.1)
* Version 1.1
* General: Support for 16bpc is added
* General: Support for 3D Audio is added
* General: Support for -1 and -2LV Devices are added
* General: Support for Native I/F is added
* General: Support for HDCP 2.3
* Revision change in one or more subcores
HDMI 2.1 Transmitter Subsystem (1.1)
* Version 1.1
* General: Support for 16bpc is added
* General: Support for 3D Audio is added
* General: Support for -1 and -2LV Devices are added
* General: Support for Native I/F is added
* General: Support for HDCP 2.3
* Revision change in one or more subcores
HDMI GT Controller (1.0)
* Version 1.0 (Rev. 3)
* General: Updated the Versal GT Reset IP to 1.1
HDMI PHY Controller (1.0)
* Version 1.0 (Rev. 2)
* General: Updated Max Rates based on Device Family
* Revision change in one or more subcores
High Speed SelectIO Wizard (3.6)
* Version 3.6 (Rev. 1)
* General: Spyglass and CDC fixes
I2S Receiver (1.0)
* Version 1.0 (Rev. 4)
* No changes
I2S Transmitter (1.0)
* Version 1.0 (Rev. 4)
* No changes
IBERT 7 Series GTH (3.0)
* Version 3.0 (Rev. 18)
* No changes
IBERT 7 Series GTP (3.0)
* Version 3.0 (Rev. 18)
* No changes
IBERT 7 Series GTX (3.0)
* Version 3.0 (Rev. 18)
* No changes
IBERT 7 Series GTZ (3.1)
* Version 3.1 (Rev. 18)
* No changes
IBERT UltraScale GTH (1.4)
* Version 1.4 (Rev. 5)
* Bug Fix: Updated constraints for new devices
* Revision change in one or more subcores
IBERT UltraScale GTM (1.0)
* Version 1.0 (Rev. 9)
* Bug Fix: Updated revision number of include file
* Revision change in one or more subcores
IBERT UltraScale GTY (1.3)
* Version 1.3 (Rev. 5)
* Revision change in one or more subcores
IEEE 802.3 200G RS-FEC (2.0)
* Version 2.0
* General: Added option to use hard block acceleration for the RS-FEC algorithm.
* Revision change in one or more subcores
IEEE 802.3 25G RS-FEC (1.0)
* Version 1.0 (Rev. 18)
* General: Updated clock wizard parameters in example design.
* Revision change in one or more subcores
IEEE 802.3 400G RS-FEC (2.0)
* Version 2.0 (Rev. 2)
* General: Corrected CDC issue
* General: Added TX codeword start output flag for GTM mode
* General: Added BROM enable input and scrubbing for ROM protection (soft decoder only)
* General: Added early "mark bad" output to reduce transcoding latency (soft decoder only)
* Revision change in one or more subcores
IEEE 802.3 50G RS-FEC (2.0)
* Version 2.0 (Rev. 6)
* General: Updated clock wizard parameters in example design.
* Revision change in one or more subcores
IEEE 802.3 Clause 74 FEC (1.0)
* Version 1.0 (Rev. 8)
* General: Updated clock wizard parameters in example design.
* Revision change in one or more subcores
IEEE 802.3 Multi-channel 25G RSFEC (1.0)
* Version 1.0 (Rev. 11)
* General: Updated device support
* Revision change in one or more subcores
IEEE 802.3bj 100G RS-FEC (2.0)
* Version 2.0 (Rev. 10)
* General: Updated clock wizard parameters in example design.
* Revision change in one or more subcores
ILA (Integrated Logic Analyzer with AXIS Interface) (1.1)
* Version 1.1 (Rev. 1)
* Feature Enhancement: Fixed timing
* Revision change in one or more subcores
ILA (Integrated Logic Analyzer) (6.2)
* Version 6.2 (Rev. 11)
* No changes
IOModule (3.1)
* Version 3.1 (Rev. 6)
* No changes
In System IBERT (1.0)
* Version 1.0 (Rev. 12)
* Revision change in one or more subcores
Interlaken 150G (2.4)
* Version 2.4 (Rev. 7)
* General: Added new device support
* Revision change in one or more subcores
Interleaver/De-interleaver (8.0)
* Version 8.0 (Rev. 15)
* No changes
JESD204 (7.2)
* Version 7.2 (Rev. 10)
* General: JESD204B UltraScale and UltraScale+ support will be discontinued at the 2021.1 release and is superseded by the JESD204C IP core.
* Revision change in one or more subcores
JESD204 PHY (4.0)
* Version 4.0 (Rev. 10)
* Bug Fix: Fixed GUI enablement of port gt_powergood on UltraScale and UltraScale+ devices when QPLL is selected.
* Feature Enhancement: Added new register (txoutclksel, address 0x524) to support TXPRBS test modes.
* Other: NA
* Revision change in one or more subcores
JESD204C (4.2)
* Version 4.2 (Rev. 3)
* Bug Fix: In Versal designs tx/rxmstresetdone and tx/rxpmaresetdone inputs from the GT Quad are now synchronized onto the s_axi_aclk domain.
* Bug Fix: Fixed a bug in the operation of CTRL_RX_BUF_ADV.
* Bug Fix: Fixed a bug which caused RX core buffer overflow when E=3 for subclass 1 in 64b66b line encoding.
* Bug Fix: Fixed a bug where EMB lock error counter did not reset with a valid frame.
* Feature Enhancement: Customized Connections option added to Block Automation in Versal designs.
* Feature Enhancement: Removed encommaalign logic from Versal block designs, not required from 2020.2 version.
* Feature Enhancement: Updated to support version 1.1 of the gt_reset_ip sub-ip core.
* Feature Enhancement: Added support for Versal GTYP transceivers.
* Other: Added Versal GT and Refclk location constraints to the example design, this removes MGTIO DRC errors.
* Revision change in one or more subcores
JTAG to AXI Master (1.2)
* Version 1.2 (Rev. 12)
* General: Updating aspartan7 support
* Revision change in one or more subcores
LDPC Encoder/Decoder (2.0)
* Version 2.0 (Rev. 6)
* Bug Fix: C model example application compilation script updated to reflect Product Guide recommended command.
* Bug Fix: Fix to example design to support Versal.
* Other: Windows C model compilation now uses Visual Studio 2017
LMB BRAM Controller (4.0)
* Version 4.0 (Rev. 19)
* Feature Enhancement: Added protocol option for frequency optimization
LPDDR3 SDRAM (MIG) (1.0)
* Version 1.0 (Rev. 10)
* General: Changes for 2020.2
* Revision change in one or more subcores
LTE DL Channel Encoder (4.0)
* Version 4.0 (Rev. 2)
* Revision change in one or more subcores
LTE Fast Fourier Transform (2.1)
* Version 2.1 (Rev. 3)
* Bug Fix: fix for GUI latency pane transform cycles
* Bug Fix: Bugfix for RFS output with cyclic prefix in streaming architecture.
* Revision change in one or more subcores
LTE PUCCH Receiver (2.0)
* Version 2.0 (Rev. 18)
* Revision change in one or more subcores
LTE RACH Detector (3.1)
* Version 3.1 (Rev. 8)
* General: Correction to pipelining of control data, which could lead to unusable output in cases where the format was reconfigured while the detector was running.
* Revision change in one or more subcores
LTE UL Channel Decoder (4.0)
* Version 4.0 (Rev. 17)
* General: Windows C model compilation now uses Visual Studio 2017
Local Memory Bus (LMB) 1.0 (3.0)
* Version 3.0 (Rev. 11)
* No changes
Lossless Compression (1.0)
* Version 1.0
* General: Initial release
MIPI CSI-2 Rx Controller (1.0)
* Version 1.0 (Rev. 8)
* No changes
MIPI CSI-2 Rx Subsystem (5.1)
* Version 5.1
* Feature Enhancement: Allows higher line rate selection for 7 Series devices
* Feature Enhancement: Added YUV420 data type (0x18) support
* Feature Enhancement: Enabled DSI path in VCK190 Application example design
* Revision change in one or more subcores
MIPI CSI-2 Tx Controller (1.0)
* Version 1.0 (Rev. 4)
* No changes
MIPI CSI-2 Tx Subsystem (2.2)
* Version 2.2
* Bug Fix: Example testbench issues fixed
* Feature Enhancement: Allows higher line rate selection for 7 Series devices
* Feature Enhancement: Example design support added for Versal devices
* Revision change in one or more subcores
MIPI D-PHY (4.3)
* Version 4.3
* Feature Enhancement: Allows higher line rate selection for 7 Series devices
* Revision change in one or more subcores
MIPI DSI Tx Controller (1.0)
* Version 1.0 (Rev. 7)
* No changes
MIPI DSI Tx Subsystem (2.2)
* Version 2.2
* Bug Fix: Fixed issue of hanging command FIFO read when command FIFO reset is asserted
* Feature Enhancement: Allows higher line rate selection for 7 Series devices
* Revision change in one or more subcores
Mailbox (2.1)
* Version 2.1 (Rev. 14)
* General: Added support for UltraRAM in Versal ACAP
Mammoth Transcoder (1.0)
* Version 1.0
* No changes
Memory Helper Core (1.4)
* Version 1.4
* No changes
Memory Interface Generator (MIG 7 Series) (4.2)
* Version 4.2 (Rev. 1)
* No changes
MicroBlaze (11.0)
* Version 11.0 (Rev. 4)
* Bug Fix: Ensure that the wdc.clear instruction takes entire cache address into account. Versions that have this issue: 10.0, 11.0, 11.0 (Rev. 1, 2, 3). Can only occur with the frequency optimized 8-stage pipeline when data cache is enabled.
* Other: Show user modified settings for the selected predefined configuration in the Vivado configuration dialog
* Other: Prevent selecting ACE bus interface together with other invalid parameters in the Vivado configuration dialog
MicroBlaze Debug Module (MDM) (3.2)
* Version 3.2 (Rev. 19)
* Feature Enhancement: Support automatic connection of external BSCAN in Versal
MicroBlaze MCS (3.0)
* Version 3.0 (Rev. 14)
* Feature Enhancement: Support automatic connection of external BSCAN in Versal
* Other: Added support for UltraRAM in Versal ACAP
* Revision change in one or more subcores
Multiplier (12.0)
* Version 12.0 (Rev. 16)
* No changes
Multiply Adder (3.0)
* Version 3.0 (Rev. 15)
* No changes
Mutex (2.1)
* Version 2.1 (Rev. 11)
* No changes
NVMe Host Accelerator (1.0)
* Version 1.0 (Rev. 3)
* Revision change in one or more subcores
NVMe Target Controller (2.0)
* Version 2.0
* General: EQDMA
* Revision change in one or more subcores
NoC Clock Re-Convergent Buffer (1.0)
* Version 1.0
* No changes
NoC NIDB (1.0)
* Version 1.0
* No changes
NoC Packet Switch (1.0)
* Version 1.0
* No changes
ORAN Radio IF (1.1)
* Version 1.1
* Bug Fix: Add interrupt bus parameter to interrupt pin
* Bug Fix: Fix reversed polarity on fram_reset_active & defm_reset_active
* Bug Fix: Fix VLAN tagged last word read and short packet support
* Bug Fix: Fixed a bug causing the state machine which is computing the deskew buffer address for a given packet to go in an unrecoverable state after receiving a VLAN tagged message out of the reception window
* Bug Fix: Fixed a bug causing partial lost of beamIDs when many component carriers are configured but not actually used
* Bug Fix: Add GTXE2 enablement
* Bug Fix: Separate timer restart to each CC timer
* Bug Fix: Stop message timestamp tvalid being asserted for all packets.
* Feature Enhancement: Added dedicated SSB data channel
* Feature Enhancement: Added symbol increment strobe option
* Feature Enhancement: Improve timer error at higher numerology
* Feature Enhancement: Timing enhancements on Circular Buffer
* Feature Enhancement: Improved the precision and efficiency of the reception window block, after such a modification the value stored in the m<E>_offset_in_symbol signal holds the exact difference between the transported symbol number and the state of the respective either downlink or uplink internal counter for U-Plane messages, while for downlink C-Plane m<E>_offset_in_symbol corresponds to such a difference minus 1 and for uplink C-Plane it is the difference minus 2
* Other: NA
PCIe AXI4-Lite_Tap (1.0)
* Version 1.0 (Rev. 1)
* Bug Fix: Fix CG write and CC read data payload format for TDATA_WIDTH=256-bit.
* Bug Fix: Fix CC Bypass payload propagation for TDATA_WIDTH=512-bit.
* Bug Fix: Support XDMA-specific point-solution handshake restrictions on Bypass pathways.
* Bug Fix: Fully pipelined Bypass pathway to support back-to-back burst traffic.
PR AXI Shutdown Manager (1.0)
* Version 1.0 (Rev. 2)
* No changes
PR Bitstream Monitor (1.0)
* Version 1.0 (Rev. 2)
* No changes
PTP 1588 Timer and Syncer (1.0)
* Version 1.0 (Rev. 1)
* Unknown category others: New feature - high accuracy mode
Partial Reconfiguration Controller (1.3)
* Version 1.3 (Rev. 4)
* No changes
Partial Reconfiguration Decoupler (1.0)
* Version 1.0 (Rev. 9)
* No changes
Peak Cancellation Crest Factor Reduction (6.4)
* Version 6.4
* Feature Enhancement: LUT optimization for all CPS cases
Platform Shell Address Remapper (1.0)
* Version 1.0 (Rev. 1)
* Bug Fix: Automate metadata propagation.
* Bug Fix: Add Wildcard Mode to allow an unspecified SI Base Addr.
* Revision change in one or more subcores
Polar Encoder/Decoder (1.0)
* Version 1.0 (Rev. 6)
* Bug Fix: Fix to bare metal driver concerning BA_TABLE address alignment for small codes.
* Bug Fix: Fix to example design to support Versal.
Processor System Reset (5.0)
* Version 5.0 (Rev. 13)
* No changes
QDRII+ SRAM (MIG) (1.4)
* Version 1.4 (Rev. 11)
* General: Updated for 2020.2
* Revision change in one or more subcores
QDRIV SRAM (MIG) (2.0)
* Version 2.0 (Rev. 10)
* General: Updated for 2020.2
* Revision change in one or more subcores
QDRIV SRAM PHY IP (2.0)
* Version 1.2
* No changes
QSGMII (3.5)
* Version 3.5
* Feature Enhancement: Updated Versal devices support
* Other: Updated with waivers in the XDC
* Revision change in one or more subcores
Queue DMA Subsystem for PCI Express (4.0)
* Version 4.0 (Rev. 2)
* Bug Fix: Updated pin constraints for ZCU117 and VCU117
* Bug Fix: Fixed the XSim simulation issue
* Bug Fix: Fixed AXI-MM performance issue
* Bug Fix: Fixed PCIE2AXI BAR address translation issue
* Other: Added XCK26 device support
* Revision change in one or more subcores
RAM-based Shift Register (12.0)
* Version 12.0 (Rev. 14)
* No changes
RAMA IP (1.1)
* Version 1.1 (Rev. 7)
* General: Updated to add support for new devices
* Revision change in one or more subcores
RLDRAM3 (MIG) (1.4)
* Version 1.4 (Rev. 10)
* General: Updated for 2020.2
* Revision change in one or more subcores
Radio over Ethernet Framer (3.0)
* Version 3.0 (Rev. 1)
* Bug Fix: Added GTXE2 support enablement.
* Feature Enhancement: None
* Other: None
Reed-Solomon Decoder (9.0)
* Version 9.0 (Rev. 17)
* No changes
Reed-Solomon Encoder (9.0)
* Version 9.0 (Rev. 16)
* No changes
Reset Verification IP (1.0)
* Version 1.0 (Rev. 4)
* No changes
SC EXIT (1.0)
* Version 1.0 (Rev. 11)
* Feature Enhancement: Distribute aresetn asynchronously among subcores to help close timing when crossing multiple SLRs.
SC MMU (1.0)
* Version 1.0 (Rev. 10)
* Feature Enhancement: Distribute aresetn asynchronously among subcores to help close timing when crossing multiple SLRs.
SC SI_CONVERTER (1.0)
* Version 1.0 (Rev. 10)
* Feature Enhancement: Distribute aresetn asynchronously among subcores to help close timing when crossing multiple SLRs.
SC SPLITTER (1.0)
* Version 1.0 (Rev. 4)
* No changes
SC TRANSACTION_REGULATOR (1.0)
* Version 1.0 (Rev. 9)
* Feature Enhancement: Distribute aresetn asynchronously among subcores to help close timing when crossing multiple SLRs.
SDI RX to Video Bridge (2.0)
* Version 2.0
* No changes
SMPTE SD/HD/3G-SDI (3.0)
* Version 3.0 (Rev. 9)
* No changes
SMPTE UHD-SDI (1.0)
* Version 1.0 (Rev. 8)
* General: Added 12G support for xc7z100 device family with speedgrade -2
SMPTE UHD-SDI RX (1.0)
* Version 1.0
* No changes
SMPTE UHD-SDI RX SUBSYSTEM (2.0)
* Version 2.0 (Rev. 6)
* New Feature: Added HDR10 support in UHD-SDI IP
* New Feature: Added VCK190 Audio-Video Example design in UHD-SDI RX Subsystem IP
* New Feature: Updated bd.xit file to propagate C_BPP parameter from rx_ss IP to UHDSDI RX IP
* New Feature: Updated KCU116 example design tcl in order to support changes accommodated in UHDSDI_GT_V2_0 IP
SMPTE UHD-SDI TX (1.0)
* Version 1.0
* No changes
SMPTE UHD-SDI TX SUBSYSTEM (2.0)
* Version 2.0 (Rev. 6)
* New Feature: Added HDR_Embedd block to support HDR 10 Feature in IP
* New Feature: Added Vsync Interrupt at bit[2] of already existing interrupt
* Revision change in one or more subcores
SPDIF/AES3 (2.0)
* Version 2.0 (Rev. 23)
* No changes
SelectIO Interface Wizard (5.1)
* Version 5.1 (Rev. 15)
* No changes
Sensor Demosaic (1.1)
* Version 1.1
* General: Added Vitis Support.
* Revision change in one or more subcores
Serial RapidIO Gen2 (4.1)
* Version 4.1 (Rev. 9)
* Revision change in one or more subcores
Shell Card Management Controller Subsystem (2.2)
* Version 1.0 (Rev. 2)
* Revision change in one or more subcores
Shell Utility Build Info (1.0)
* Version 1.0
* No changes
Shell Utility MSP432 BSL CRC Generator (1.0)
* Version 1.0
* No changes
Slice (1.0)
* Version 1.0 (Rev. 2)
* No changes
SmartConnect AXI2SC Bridge (1.0)
* Version 1.0 (Rev. 7)
* No changes
SmartConnect NOC Entry Bridge (1.0)
* Version 1.0
* No changes
SmartConnect NOC Exit Bridge (1.0)
* Version 1.0
* No changes
SmartConnect NOC Router (1.0)
* Version 1.0
* No changes
SmartConnect Node (1.0)
* Version 1.0 (Rev. 12)
* Feature Enhancement: Add priority arbitration option
* Feature Enhancement: Distribute aresetn asynchronously among subcores to help close timing when crossing multiple SLRs.
SmartConnect SC2AXI Bridge (1.0)
* Version 1.0 (Rev. 7)
* No changes
SmartConnect Switchboard (1.0)
* Version 1.0 (Rev. 6)
* No changes
Soft ECC Proxy (1.0)
* Version 1.0
* No changes
Soft Error Mitigation (4.1)
* Version 4.1 (Rev. 13)
* No changes
Soft-Decision FEC (1.1)
* Version 1.1 (Rev. 6)
* General: Example design updated to use board support package.
Stream Traffic Manager (1.0)
* Version 1.0
* No changes
Switch Core Top (1.0)
* Version 1.0 (Rev. 8)
* No changes
System Cache (5.0)
* Version 5.0 (Rev. 3)
* Port Change: Added CHI ports
* Bug Fix: Corrected CCIX Coherency tab in Vivado configuration dialog to use correct parameter for "Keep After SnpToC" and remove "Pass Dirty After SnpToC"
* Bug Fix: Prevent CCIX MPS overrun with chaining enabled.
* Bug Fix: Fixed CCIX tag corruption caused by stalling CleanShared being invalidated by snoop.
* Bug Fix: Avoid CCIX message race condition between memory requests and snoop response with snoop filter support enabled.
* Bug Fix: Fixed CCIX state transition for WriteCleanFull when initiating FCWriteCleanFull via the AXI control interface.
* Bug Fix: Fixed CCIX multiple requests with initial message Evict with snoop filter support enabled.
* Feature Enhancement: Added support for CHI coherency protocol
System ILA (1.1)
* Version 1.1 (Rev. 8)
* General: Updating aspartan7 support
* Revision change in one or more subcores
System Management Wizard (1.3)
* Version 1.3 (Rev. 13)
* General: Device updates.
TMR Comparator (1.0)
* Version 1.0 (Rev. 4)
* Bug Fix: Set the RTL trace size parameter according to the user assigned value
TMR Inject (1.0)
* Version 1.0 (Rev. 4)
* No changes
TMR Manager (1.0)
* Version 1.0 (Rev. 6)
* General: Improvement of reset handling, no functional changes
TMR Soft Error Mitigation Interface (1.0)
* Version 1.0 (Rev. 15)
* Bug Fix: Included definitions for all supported UltraScale and UltraScale+ devices
* Revision change in one or more subcores
TMR Voter (1.0)
* Version 1.0 (Rev. 3)
* No changes
TSN Endpoint Block (1.0)
* Version 1.0 (Rev. 7)
* Revision change in one or more subcores
TSN Tri Mode Ethernet MAC (1.0)
* Version 1.0 (Rev. 5)
* No changes
Time-Aware DMA (1.0)
* Version 1.0 (Rev. 6)
* Revision change in one or more subcores
Timer Sync 1588 (1.2)
* Version 1.2 (Rev. 4)
* No changes
Trace S2MM (1.0)
* Version 1.0
* No changes
Tri Mode Ethernet MAC (9.0)
* Version 9.0 (Rev. 17)
* Bug Fix: Fixed TIMING-10 Methodology violations
* Other: Spartan-7 device families marked production
* Other: Added waivers for safe CDC violation messages
UHD-SDI Audio (2.0)
* Version 2.0 (Rev. 3)
* General: Enabled for Versal Devices
UHD-SDI GT (2.0)
* Version 2.0 (Rev. 3)
* Bug Fix: Fixed issue QPLL1 is not connected in the RTL when selecting the GTY and 12G-SDI (AR75505)
* Bug Fix: Fixed issue QPLL0 is not selected in the UHD-SDI GT TX (AR75505)
* Bug Fix: Fixed issues found in verification for multiple
* New Feature: Removed CPLL refclk selection from GUI
* New Feature: Added SDI design notes in GUI for Ease of Use
* Revision change in one or more subcores
UHD-SDI Video Pattern Generator (1.0)
* Version 1.0 (Rev. 1)
* No changes
URAM Read Back (1.0)
* Version 1.0 (Rev. 1)
* Feature Enhancement: BUFGCTRL Removed from IP
* Feature Enhancement: Extra commands added in read back FSM of IP (Start, Restore, Exit).
* Feature Enhancement: Parameter Configurable option added for URAM Input register with default as No register stage.
UltraScale 100G Ethernet Subsystem (2.6)
* Version 2.6 (Rev. 2)
* General: Added ctl_an_reset signal with AXI4 register write to provide the soft reset to ANLT module
* Revision change in one or more subcores
UltraScale FPGA Gen3 Integrated Block for PCI Express (4.4)
* Version 4.4 (Rev. 9)
* General: Added civ devices vu440,ku115
* Revision change in one or more subcores
UltraScale FPGAs Transceivers Wizard (1.7)
* Version 1.7 (Rev. 9)
* General: Added new transceiver configuration preset options for VbyOne
UltraScale Soft Error Mitigation (3.1)
* Version 3.1 (Rev. 16)
* General: Added support for VU19P,VU15P,VU23P and additional UltraScale+ devices
UltraScale+ 100G Ethernet Subsystem (3.1)
* Version 3.1 (Rev. 2)
* General: Added ctl_an_reset signal with AXI4 register write to provide the soft reset to ANLT module
* General: Added new UltraScale+ devices support
* Revision change in one or more subcores
UltraScale+ Integrated Block (PCIE4) for PCI Express (1.3)
* Version 1.3 (Rev. 9)
* Bug Fix: Fixed TXOUTCLK constraining issue, which exists in the last release.
* Feature Enhancement: Added XCK26 device support.
* Other: Constraining only Master lane TXOUTCLK, instead constraining on all lanes.
* Other: Updated IBUFDS_GTE4 parameters for 250 MHz reference clock designs
* Other: Fixed few IP related warnings, which do not alter IP functionality.
* Revision change in one or more subcores
UltraScale+ Integrated Block (PCIE4C) for PCI Express (1.0)
* Version 1.0 (Rev. 10)
* Bug Fix: Fixed the intermittent config read hang in Bridge Mode Root Port config
* Bug Fix: Fixed VU19P device support issue
* Bug Fix: Fixed TXOUTCLK constraining issue, which exists in the last release.
* Other: Added XCZU43DR and XCVU57P device support.
* Other: Updated IBUFDS_GTE4 parameters for 250 MHz reference clock designs
* Other: Fixed few IP related warnings, which do not alter IP functionality.
* Revision change in one or more subcores
UltraScale+ PHY for PCI Express (1.0)
* Version 1.0 (Rev. 15)
* Bug Fix: Fixed phy_rxdata stuck at zero issue in Gen4 example design simulation
* Bug Fix: RST_TXPROGDIVRESET fix is added.
* Revision change in one or more subcores
Universal Serial XGMII Ethernet Subsystem (1.2)
* Version 1.2
* Bug Fix: Fixed Methodology violations
* Bug Fix: Updated the axis_rx ports associated clocks
* Other: Added support for IP waivers in the XDC
* Other: Added Versal devices support
* Other: Added support for new device
* Revision change in one or more subcores
Utility Reduced Logic (2.0)
* Version 2.0 (Rev. 4)
* No changes
Utility Vector Logic (2.0)
* Version 2.0 (Rev. 1)
* No changes
VIO (Virtual Input/Output with AXIS Interface) (1.0)
* Version 1.0 (Rev. 2)
* General: Fixed CDC issues
VIO (Virtual Input/Output) (3.0)
* Version 3.0 (Rev. 19)
* No changes
Versal ACAP Integrated Block for PCI Express (1.0)
* Version 1.0 (Rev. 3)
* Bug Fix: fixed cs_server exception issue after reboot
* Bug Fix: fixed SIM_DEVICE settings for PCIE40E5 & PCIE50E5
* Feature Enhancement: gt_quad_base updated from v1.0 to v1.1
* Revision change in one or more subcores
Versal ACAP PHY for PCI Express (1.0)
* Version 1.0 (Rev. 3)
* Bug Fix: Fixed phy_rxdata stuck at zero issue in Gen4 example design simulation
* Bug Fix: Fixed pattern generation in Gen4
* Feature Enhancement: gt_quad_base updated from v1.0 to v1.1
Versal ACAP XDMA Subsystem for PCI Express (2.0)
* Version 2.0 (Rev. 1)
* Feature Enhancement: Enabled M_AXI_LITE interface when AXI_Lite Master is enabled for AXI Bridge mode.
* Feature Enhancement: gt_quad_base updated from v1.0 to v1.1
* Feature Enhancement: QDMA, AXI_Bridge-EP and AXI_Bridge-Rootport modes deprecated.
* Revision change in one or more subcores
Versal ACAPs Transceivers Bridge IP (1.1)
* Version 1.1
* General: Added VbyOne Protocol PRESET
* General: Individual DATAPATH reset ports added to the IP
* General: Flexible lane selection feature added to the Block Automation support
* Revision change in one or more subcores
Versal ACAPs Transceivers Reset IP (1.1)
* Version 1.1
* General: The FSM logic is modified for Master Reset mode to support individual datapath reset functionality
Versal ACAPs Transceivers Wizard (1.1)
* Version 1.1
* Feature Enhancement: Added VbyOne protocol PRESET
* Feature Enhancement: Added ports to enable DATAPATH reset in MASTER RESET mode
* Revision change in one or more subcores
Versal DDR4 Memory Controller (1.0)
* Version 1.0 (Rev. 2)
* Bug Fix: PLM Time out value fix for Memory initialization
* Feature Enhancement: Clamshell support
* Feature Enhancement: 3DS x8 component width support
* Feature Enhancement: support for DDP wide parts
* Feature Enhancement: Future expansion for PCB designs per MC support
Versal QDRIV SRAM (1.0)
* Version 1.0 (Rev. 2)
* No changes for 2020.2
* Revision change in one or more subcores
Versal Soft DDR4 Memory Controller (1.0)
* Version 1.0 (Rev. 3)
* Supported Bit-Wise Address Mapping options
* Supported Restore CRC
* 3DS - x8 component width support
* GUI support to differentiate between DDP Deep and DDP wide Components
* Revision change in one or more subcores
Versal Soft RLDRAM3 Memory Controller (1.0)
* Version 1.0 (Rev. 4)
* No changes in 2020.2
* Revision change in one or more subcores
Video AXI4S Remapper (1.1)
* Version 1.1
* General: Revision change in one or more subcores.
* General: Added Vitis Support
* Revision change in one or more subcores
Video Color Space Conversion and Correction (1.1)
* Version 1.1
* General: Added Vitis Support
* Revision change in one or more subcores
Video Deinterlacer (5.1)
* Version 2.2
* General: Added Vitis Support
* Revision change in one or more subcores
Video DisplayPort 1.4 RX Subsystem (3.0)
* Version 3.0
* New Feature: Added YUV420 support
* New Feature: Colorimetry decoding using VSC SDP packet in addition to MISC0/1 MSA values
* New Feature: Added adaptive-sync feature, adaptive-sync SDP packet reception along with interrupt generation
* New Feature: Added fabric 8B10B decoder implementation
* New Feature: Added In-band 3D stereo display protocol support
* New Feature: Added aux burst read support for lane status DPCD registers
* New Feature: Supported devices and production status are now determined automatically, to simplify support for future devices
* Revision change in one or more subcores
Video DisplayPort 1.4 TX Subsystem (3.0)
* Version 3.0
* New Feature: Added YUV420 support
* New Feature: Colorimetry support using VSC SDP packet in addition to MISC0/1 MSA values
* New Feature: Added adaptive-sync feature
* New Feature: Added support to program two INFOFRAME packets per frame and enhanced to store and transmit 4 INFO packets
* New Feature: Added fabric 8B10B encoder implementation
* New Feature: Added In-band 3D stereo display protocol support
* New Feature: Supported devices and production status are now determined automatically, to simplify support for future devices
* Revision change in one or more subcores
Video Frame Buffer Read (2.2)
* Version 2.2
* General: Added Vitis Support
* General: Added support for XY10 data using XYAVTA tool
* Revision change in one or more subcores
Video Frame Buffer Write (2.2)
* Version 2.2
* Feature Enhancement: Added support for XY10 data using XYAVTA tool
* Other: Added Vitis Support
* Revision change in one or more subcores
Video Horizontal Chroma Resampler (1.1)
* Version 1.1
* General: Added Vitis Support
* Revision change in one or more subcores
Video Horizontal Scaler (1.1)
* Version 1.1
* General: Added Vitis Support
* Revision change in one or more subcores
Video In to AXI4-Stream (4.0)
* Version 4.0 (Rev. 9)
* No changes
Video Letterbox Engine (1.1)
* Version 1.1
* General: Added Vitis Support
* Revision change in one or more subcores
Video Mixer (5.1)
* Version 5.1
* General: Added Vitis Support
* Revision change in one or more subcores
Video Multi-Scaler (1.2)
* Version 1.2
* General: Added Vitis Support
* Revision change in one or more subcores
Video PHY Controller (2.2)
* Version 2.2 (Rev. 7)
* General: Clock Filter delta parameter can be accessed through AXI Lite IF through 0x200 register.
* General: When upgrading VPHY IP from 2018.3 you might miss the constraints, please check the Product Guide for mode details.
* Revision change in one or more subcores
Video Processing Subsystem (2.3)
* Version 2.3
* General: Added Vitis Support
* Revision change in one or more subcores
Video Scene Change Detection (1.1)
* Version 1.1
* General: Added Vitis Support
* Revision change in one or more subcores
Video Test Pattern Generator (8.1)
* Version 8.1
* General: Added Vitis Support
* Revision change in one or more subcores
Video Timing Controller (6.2)
* Version 6.2 (Rev. 1)
* General: Adaptive Sync support for DisplayPort TX SS
Video Vertical Chroma Resampler (1.1)
* Version 1.1
* General: Added Vitis Support
* Revision change in one or more subcores
Video Vertical Scaler (1.1)
* Version 1.1
* General: Added Vitis Support
* Revision change in one or more subcores
Video to SDI TX Bridge (2.0)
* Version 2.0
* No changes
Virtex UltraScale+ FPGAs GTM Transceivers Wizard (1.0)
* Version 1.0 (Rev. 9)
* General: Added support for XCVU23P devices
* Revision change in one or more subcores
Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.3)
* Version 4.3 (Rev. 9)
* General: Tied unused pipe TX and RX signals to zero for CIV data rate check, DRC check.
Viterbi Decoder (9.1)
* Version 9.1 (Rev. 12)
* No changes
XADC Wizard (3.3)
* Version 3.3 (Rev. 8)
* No changes
XHMC (1.0)
* Version 1.0 (Rev. 12)
* Revision change in one or more subcores
ZYNQ UltraScale+ SYNC IP (1.0)
* Version 1.0 (Rev. 4)
* Revision change in one or more subcores
ZYNQ UltraScale+ VCU (1.2)
* Version 1.2 (Rev. 2)
* No changes
ZYNQ UltraScale+ VCU DDR4 Controller (1.1)
* Version 1.1 (Rev. 2)
* Port Change: NONE
* Bug Fix: NONE
* Feature Enhancement: New RAM MT40A256M16-062E is added
* Other: NONE
* Revision change in one or more subcores
ZYNQ7 Processing System (5.5)
* Version 5.5 (Rev. 6)
* No changes
ZYNQ7 Processing System VIP (1.0)
* Version 1.0 (Rev. 10)
* Revision change in one or more subcores
ZYNQMPSOC Processing System VIP (1.0)
* Version 1.0 (Rev. 8)
* Revision change in one or more subcores
Zynq UltraScale+ MPSoC (3.3)
* Version 3.3 (Rev. 3)
* Bug Fix: 1.Added response queues for READ/Write transactions for Slave interfaces.
* Revision change in one or more subcores
Zynq UltraScale+ RF Data Converter (2.4)
* Version 2.4
* Bug Fix: Fixed gen 3 RF-DAC PLL settings
* Bug Fix: Optimized clock forwarding for gen 3 devices
* Bug Fix: Fixed datapath mode programming for multi-band configurations in gen 3 dual DAC devices
* Bug Fix: Fixed calibration mode comment in IP GUI
* Bug Fix: Fixed DAC data path mode comment in IP GUI
* Bug Fix: Fixed SYSREF gate real time input on gen 3 ADC
* New Feature: Added ADC observation interface for gen 3 devices
* New Feature: Added support for gen 3 production devices
* New Feature: Added support for gen 3 autocal option
* New Feature: Added support for gen 3 TDD real time signal interface
* Other: Updated clock distribution options in gen 3 devices
* Other: Updated sample rate limits for -1 speed grade gen3 devices
* Other: Optimized calibration process in gen 3 devices
* Other: Modified DAC VOP real time signal interface to assert done when the update of each individual channel has completed
* Other: Reduced power consumption of gen 3 quad ADC tiles when in the shut down state
* Other: Updated DAC clocking in the demonstration testbench
* Other: Turned Questa optimization off for example design simulations to avoid DAC output corruption
audio_tpg_v1_0 (1.0)
* Version 1.0
* No changes
axi_msg (1.0)
* Version 1.0 (Rev. 6)
* No changes
axi_sg (4.1)
* Version 4.1 (Rev. 13)
* No changes
gt_subcore_ip_v1_0 (1.0)
* Version 1.0 (Rev. 3)
* General: Added VbyOne protocol PRESET
* General: Ethernet PRESET configurations have been updated
gtm_cntrl (1.0)
* Version 1.0 (Rev. 6)
* General: Added support for XCVU23P devices
* Revision change in one or more subcores
interrupt_controller (3.1)
* Version 3.1 (Rev. 4)
* No changes
lib_bmg (1.0)
* Version 1.0 (Rev. 13)
* No changes
lib_cdc (1.0)
* Version 1.0 (Rev. 2)
* No changes
lib_fifo (1.0)
* Version 1.0 (Rev. 14)
* No changes
lib_pkg (1.0)
* Version 1.0 (Rev. 2)
* No changes
lib_srl_fifo (1.0)
* Version 1.0 (Rev. 2)
* No changes
| AR# 75786 | |
|---|---|
| 日期 | 11/25/2020 |
| 状态 | Active |
| Type | 版本说明 |
| Tools | |