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10G Ethernet MAC (15.1)
* Version 15.1 (Rev. 1)
* Revision change in one or more subcores
10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)
* Version 6.0 (Rev. 5)
* Fix for registers related to lp_coeff_update_status, lp_coeff_initialize_status and lp_coeff_preset_status
* Revision change in one or more subcores
10G Ethernet Subsystem (3.1)
* Version 3.1 (Rev. 1)
* No Functional changes.
* Revision change in one or more subcores
10G/25G Ethernet Subsystem (1.3)
* Version 1.3
* Runtime Swithcable support for UltraScale+ added
* Support added support for xqku115 and 1M speed grade
* GT Out of Core Support
* Revision change in one or more subcores
1G/2.5G Ethernet PCS/PMA or SGMII (15.2)
* Version 15.2 (Rev. 1)
* Bugfix for extra port required by GT Wizard for older UltraScale devices which used calibration logic.
* Revision change in one or more subcores
32-bit Initiator/Target for PCI (7-Series) (5.0)
* Version 5.0 (Rev. 8)
* No changes
3GPP LTE Channel Estimator (2.0)
* Version 2.0 (Rev. 11)
* No changes
3GPP LTE MIMO Decoder (3.0)
* Version 3.0 (Rev. 11)
* No changes
3GPP LTE MIMO Encoder (4.0)
* Version 4.0 (Rev. 10)
* No changes
3GPP Mixed Mode Turbo Decoder (2.0)
* Version 2.0 (Rev. 11)
* No changes
3GPP Turbo Encoder (5.0)
* Version 5.0 (Rev. 10)
* No changes
3GPPLTE Turbo Encoder (4.0)
* Version 4.0 (Rev. 10)
* No changes
40G/50G Ethernet Subsystem (1.1)
* Version 1.1
* Support for IPI
* Support for 50G 2 core
* Revision change in one or more subcores
64-bit Initiator/Target for PCI (7-Series) (5.0)
* Version 5.0 (Rev. 8)
* No changes
7 Series FPGAs Transceivers Wizard (3.6)
* Version 3.6 (Rev. 3)
* COMMON_CFG[6] attribute value updated for configurations with QPLL on GTH transceiver based devices
7 Series Integrated Block for PCI Express (3.3)
* Version 3.3 (Rev. 1)
* Reduced the number of characters on a single line by making a multi-line attribute assignment.
* Added CDC registers to the pl_phy_lnk_up and pl_received_hot_rst PCIe outputs.
* Revision change in one or more subcores
AHB-Lite to AXI Bridge (3.0)
* Version 3.0 (Rev. 7)
* Revision change in one or more subcores
AXI 1G/2.5G Ethernet Subsystem (7.0)
* Version 7.0 (Rev. 5)
* Support GT in Example Design.
* Revision change in one or more subcores
AXI AHB Lite Bridge (3.0)
* Version 3.0 (Rev. 7)
* Revision change in one or more subcores
AXI APB Bridge (3.0)
* Version 3.0 (Rev. 7)
* Revision change in one or more subcores
AXI BFM Cores (5.0)
* Version 5.0 (Rev. 7)
* No changes
AXI BRAM Controller (4.0)
* Version 4.0 (Rev. 8)
* Revision change in one or more subcores
AXI Bridge for PCI Express Gen3 Subsystem (2.1)
* Version 2.1 (Rev. 1)
* Updated the Tandem with Field Updates example design scripts to reference the appropriate constraints file when a development board is selected in the project settings.
* Updated the Tandem with Field Updates example design scripts to handle IP core containers where the output products were not generated.
* Added support for defense grade Kintex UltraScale device xqku115
* Modified the insertion loss profile parameter to provide three options Chip-to-Chip(5db), Add-in_Card(15db) and Backplane(20db). Core operates in LPM mode for the values < 15db and DFE mode for the values >= 15db.
* Revision change in one or more subcores
AXI CAN (5.0)
* Version 5.0 (Rev. 12)
* Revision change in one or more subcores
AXI Central Direct Memory Access (4.1)
* Version 4.1 (Rev. 9)
* Revision change in one or more subcores
AXI Chip2Chip Bridge (4.2)
* Version 4.2 (Rev. 9)
* Revision change in one or more subcores
AXI Clock Converter (2.1)
* Version 2.1 (Rev. 8)
* Update IP clocking XDC to cover asynchronous CDC used by FIFO Generator v13.x.
* Revision change in one or more subcores
AXI Crossbar (2.1)
* Version 2.1 (Rev. 10)
* Improved automation in Vivado IP Integrator to allow propagation of more AXI interface properties.
* Revision change in one or more subcores
AXI Data FIFO (2.1)
* Version 2.1 (Rev. 8)
* Revision change in one or more subcores
AXI Data Width Converter (2.1)
* Version 2.1 (Rev. 9)
* Update IP clocking XDC to cover asynchronous CDC used by FIFO Generator v13.x.
* Revision change in one or more subcores
AXI DataMover (5.1)
* Version 5.1 (Rev. 11)
* Enhanced support for IP Integrator. No functional changes
* Revision change in one or more subcores
AXI Direct Memory Access (7.1)
* Version 7.1 (Rev. 10)
* Revision change in one or more subcores
AXI EMC (3.0)
* Version 3.0 (Rev. 9)
* Interface definition updated. No functional changes
* Revision change in one or more subcores
AXI EPC (2.0)
* Version 2.0 (Rev. 12)
* Revision change in one or more subcores
AXI Ethernet Buffer (2.0)
* Version 2.0 (Rev. 12)
* Revision change in one or more subcores
AXI Ethernet Clocking (2.0)
* Version 2.0 (Rev. 2)
* No changes
AXI Ethernet Lite (3.0)
* Version 3.0 (Rev. 7)
* Revision change in one or more subcores
AXI GPIO (2.0)
* Version 2.0 (Rev. 11)
* Revision change in one or more subcores
AXI HWICAP (3.0)
* Version 3.0 (Rev. 13)
* Precompiled library required changes. No functional changes
* Revision change in one or more subcores
AXI IIC (2.0)
* Version 2.0 (Rev. 12)
* Revision change in one or more subcores
AXI Interconnect (2.1)
* Version 2.1 (Rev. 10)
* Revision change in one or more subcores
AXI Interrupt Controller (4.1)
* Version 4.1 (Rev. 7)
* Provided register information for all registers, including description and bit field definitions
* Revision change in one or more subcores
AXI Lite IPIF (3.0)
* Version 3.0 (Rev. 4)
* Internal variable name update, No functional changes
AXI MMU (2.1)
* Version 2.1 (Rev. 7)
* Revision change in one or more subcores
AXI Master Burst (2.0)
* Version 2.0 (Rev. 7)
* No changes
AXI Memory Mapped To PCI Express (2.8)
* Version 2.8 (Rev. 1)
* Fixed delta delay mismatch between axi_aclk and axi_ctl_aclk clock domains in simulation environment
* Revision change in one or more subcores
AXI Memory Mapped to Stream Mapper (1.1)
* Version 1.1 (Rev. 8)
* Revision change in one or more subcores
AXI Performance Monitor (5.0)
* Version 5.0 (Rev. 11)
* Clock and reset interface definitions added to external clock and reset
* Control register added dynamically on and off trace traffic
* Revision change in one or more subcores
AXI Protocol Checker (1.1)
* Version 1.1 (Rev. 10)
* Revision change in one or more subcores
AXI Protocol Converter (2.1)
* Version 2.1 (Rev. 9)
* Improved automation in Vivado IP Integrator to allow propagation of more AXI interface properties.
* Revision change in one or more subcores
AXI Quad SPI (3.2)
* Version 3.2 (Rev. 8)
* Interface definition updated. No functional changes
* Revision change in one or more subcores
AXI Register Slice (2.1)
* Version 2.1 (Rev. 9)
* Add "SI_Reg" and "MI_Reg" (type 9) reg_config mode (source-side completely registered)
* Add ENABLE_BURST/SIZE user-parameters
* Revision change in one or more subcores
AXI SmartConnect (1.0)
* Version 1.0 (Rev. 1)
* Added change log file.
* Resolved various bugs.
* Revision change in one or more subcores
AXI TFT Controller (2.0)
* Version 2.0 (Rev. 13)
* Revision change in one or more subcores
AXI Timebase Watchdog Timer (3.0)
* Version 3.0 (Rev. 1)
* Revision change in one or more subcores
AXI Timer (2.0)
* Version 2.0 (Rev. 11)
* Revision change in one or more subcores
AXI Traffic Generator (2.0)
* Version 2.0 (Rev. 10)
* 16bit write and read channel user signal width support added in AXI-Full mode.
* Fanout reduction for better timing
* Revision change in one or more subcores
AXI UART16550 (2.0)
* Version 2.0 (Rev. 11)
* Revision change in one or more subcores
AXI USB2 Device (5.0)
* Version 5.0 (Rev. 10)
* Revision change in one or more subcores
AXI Uartlite (2.0)
* Version 2.0 (Rev. 13)
* Revision change in one or more subcores
AXI Video Direct Memory Access (6.2)
* Version 6.2 (Rev. 8)
* Enhanced support for IP Integrator, no functional changes
* Revision change in one or more subcores
AXI Virtual FIFO Controller (2.0)
* Version 2.0 (Rev. 11)
* Revision change in one or more subcores
AXI-Stream FIFO (4.1)
* Version 4.1 (Rev. 6)
* Revision change in one or more subcores
AXI4-Stream Accelerator Adapter (2.1)
* Version 2.1 (Rev. 8)
* Revision change in one or more subcores
AXI4-Stream Broadcaster (1.1)
* Version 1.1 (Rev. 9)
* Revision change in one or more subcores
AXI4-Stream Clock Converter (1.1)
* Version 1.1 (Rev. 10)
* Revision change in one or more subcores
AXI4-Stream Combiner (1.1)
* Version 1.1 (Rev. 8)
* Revision change in one or more subcores
AXI4-Stream Data FIFO (1.1)
* Version 1.1 (Rev. 10)
* Revision change in one or more subcores
AXI4-Stream Data Width Converter (1.1)
* Version 1.1 (Rev. 8)
* Revision change in one or more subcores
AXI4-Stream Interconnect (2.1)
* Version 2.1 (Rev. 10)
* Revision change in one or more subcores
AXI4-Stream Protocol Checker (1.1)
* Version 1.1 (Rev. 9)
* Revision change in one or more subcores
AXI4-Stream Register Slice (1.1)
* Version 1.1 (Rev. 9)
* Revision change in one or more subcores
AXI4-Stream Subset Converter (1.1)
* Version 1.1 (Rev. 9)
* Revision change in one or more subcores
AXI4-Stream Switch (1.1)
* Version 1.1 (Rev. 9)
* Revision change in one or more subcores
AXI4-Stream to Video Out (4.0)
* Version 4.0 (Rev. 3)
* Revision change in one or more subcores
Accumulator (12.0)
* Version 12.0 (Rev. 9)
* No changes
Adder/Subtracter (12.0)
* Version 12.0 (Rev. 9)
* No changes
Aurora 64B66B (11.1)
* Version 11.1 (Rev. 1)
* COMMON_CFG[6] attribute value updated for configurations with QPLL on GTHE2 Transceiver based devices
* Revision change in one or more subcores
Aurora 8B10B (11.0)
* Version 11.0 (Rev. 5)
* Fixed Artix7 periodic channel up toggle issue
* Revision change in one or more subcores
Binary Counter (12.0)
* Version 12.0 (Rev. 9)
* No changes
Block Memory Generator (8.3)
* Version 8.3 (Rev. 3)
* updated the IP, not to set WRITE_DEPTH parameter to 8192 every time when the mode is switched to BRAM_Controller
* Updated the IP to support the device package changes
CANFD (1.0)
* Version 1.0 (Rev. 2)
* Revision change in one or more subcores
CIC Compiler (4.0)
* Version 4.0 (Rev. 10)
* No changes
CORDIC (6.0)
* Version 6.0 (Rev. 10)
* No changes
CPRI (8.6)
* Version 8.6 (Rev. 1)
* Added support for qkintexu parts.
* Fixed issue where the core sticks in the L1 synchronization state after a soft reset.
* Revision change in one or more subcores
Chroma Resampler (4.0)
* Version 4.0 (Rev. 9)
* Revision change in one or more subcores
Clocking Wizard (5.3)
* Version 5.3 (Rev. 1)
* Internal register bit update, no effect on customer designs.
Color Correction Matrix (6.0)
* Version 6.0 (Rev. 10)
* Revision change in one or more subcores
Color Filter Array Interpolation (7.0)
* Version 7.0 (Rev. 9)
* Revision change in one or more subcores
Complex Multiplier (6.0)
* Version 6.0 (Rev. 11)
* No changes
Convolution Encoder (9.0)
* Version 9.0 (Rev. 10)
* No changes
DDR3 SDRAM (MIG) (1.2)
* Version 1.2 (Rev. 1)
* Updated for 2016.2
* Revision change in one or more subcores
DDR4 SDRAM (MIG) (2.0)
* Version 2.0 (Rev. 1)
* Updated for 2016.2
* Revision change in one or more subcores
DDS Compiler (6.0)
* Version 6.0 (Rev. 12)
* No changes
DMA Subsystem for PCI Express (PCIe) (2.0)
* Version 2.0 (Rev. 1)
* Fixed issue with the generation of acknowledgement for interrupt assertion and de-assertion when multiple interrupts are generated.
* Removed the GUI selections for AXI Data Widths that are not supported for -1 speedgrade parts.
* Updated the Tandem with Field Updates example design scripts to handle IP core containers where the output products were not generated.
* Added support for defense grade Kintex UltraScale device xqku115
* Modified the insertion loss profile parameter to provide three options Chip-to-Chip(5db), Add-in_Card(15db) and Backplane(20db). Core operates in LPM mode for the values < 15db and DFE mode for the values >= 15db.
* Revision change in one or more subcores
DSP48 Macro (3.0)
* Version 3.0 (Rev. 12)
* No changes
DUC/DDC Compiler (3.0)
* Version 3.0 (Rev. 10)
* No changes
Debug Bridge (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
Decapsulator (1.0)
* Version 1.0 (Rev. 1)
* core update for Vivado tool compatibility
* Revision change in one or more subcores
Discrete Fourier Transform (4.0)
* Version 4.0 (Rev. 11)
* No changes
DisplayPort (7.0)
* Version 7.0 (Rev. 1)
* Fixed audio time stamp packet ECC calculation issue in DisplayPort TX
* Fixed 4-Byte audio interop issues seen in RX
* Changed Bi directional AUXIO property in UltraScale family from LVDS_25 to LVDS
* Fixed 4-Byte MST TX issue of sending extra pixel
* Fixed the issue of incorrect value over lnk_n_vid port in RX
* Revision change in one or more subcores
DisplayPort RX Subsystem (2.0)
* Version 2.0 (Rev. 1)
* Revision change in one or more subcores
DisplayPort TX Subsystem (2.0)
* Version 2.0 (Rev. 1)
* Revision change in one or more subcores
Distributed Memory Generator (8.0)
* Version 8.0 (Rev. 10)
* No changes
Divider Generator (5.1)
* Version 5.1 (Rev. 10)
* No changes
ECC (2.0)
* Version 2.0 (Rev. 11)
* No changes
Ethernet PHY MII to Reduced MII (2.0)
* Version 2.0 (Rev. 11)
* Revision change in one or more subcores
FIFO Generator (13.1)
* Version 13.1 (Rev. 1)
* Revision change in one or more subcores
FIR Compiler (7.2)
* Version 7.2 (Rev. 6)
* No changes
Fast Fourier Transform (9.0)
* Version 9.0 (Rev. 10)
* No changes
Fixed Interval Timer (2.0)
* Version 2.0 (Rev. 7)
* No changes
Floating-point (7.1)
* Version 7.1 (Rev. 2)
* No changes
Framer (1.0)
* Version 1.0 (Rev. 1)
* core update for Vivado tool compatibility
G.709 FEC Encoder/Decoder (2.2)
* Version 2.2 (Rev. 4)
* Removal of superfluous clock enable to OTN interfaces. No change in behavior.
* Revision change in one or more subcores
G.975.1 EFEC I.4 Encoder/Decoder (1.0)
* Version 1.0 (Rev. 12)
* No changes
G.975.1 EFEC I.7 Encoder/Decoder (2.0)
* Version 2.0 (Rev. 12)
* No changes
Gamma Correction (7.0)
* Version 7.0 (Rev. 10)
* Revision change in one or more subcores
Gmii to Rgmii (4.0)
* Version 4.0 (Rev. 3)
* No changes
HDCP (1.0)
* Version 1.0 (Rev. 1)
* No changes
HDCP 2.2 Cipher (1.0)
* Version 1.0
* No changes
HDCP 2.2 Montgomery Modular Multipler (1.0)
* Version 1.0
* No changes
HDCP 2.2 Random Number Generator (1.0)
* Version 1.0
* No changes
HDCP 2.2 Receiver (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
HDCP 2.2 Transmitter (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
HDMI 1.4/2.0 Receiver (1.1)
* Version 1.1
* No changes
HDMI 1.4/2.0 Receiver Subsystem (2.0)
* Version 2.0 (Rev. 1)
* Added option to Enable/Disable Remapper
* Added HDCP mode bit and HDCP 1.4 short read to DDC peripheral
* Fixed the missing Preamble for all Audio Channel Pairs
* Fixed issue with image flickering and wrong display image
* Revision change in one or more subcores
HDMI 1.4/2.0 Transmitter (1.1)
* Version 1.1
* No changes
HDMI 1.4/2.0 Transmitter Subsystem (2.0)
* Version 2.0 (Rev. 1)
* Added option to Enable/Disable Remapper
* Revision change in one or more subcores
High Speed SelectIO Wizard (3.0)
* Version 3.0
* No changes
IBERT 7 Series GTH (3.0)
* Version 3.0 (Rev. 13)
* Revision change in one or more subcores
IBERT 7 Series GTP (3.0)
* Version 3.0 (Rev. 12)
* Revision change in one or more subcores
IBERT 7 Series GTX (3.0)
* Version 3.0 (Rev. 13)
* Revision change in one or more subcores
IBERT 7 Series GTZ (3.1)
* Version 3.1 (Rev. 10)
* Revision change in one or more subcores
* Updated module names and retained few signal names
IBERT UltraScale GTH (1.3)
* Version 1.3 (Rev. 3)
* Removed system clock pin lock update dependency on its IO standard.
* Revision change in one or more subcores
IBERT UltraScale GTY (1.2)
* Version 1.2 (Rev. 3)
* Removed system clock pin lock update dependency on its IO standard.
* Revision change in one or more subcores
IEEE 802.3 25G RS-FEC (1.0)
* Version 1.0 (Rev. 1)
* Adds support for KU3P devices.
* Revision change in one or more subcores
IEEE 802.3 50G RS-FEC (1.0)
* Version 1.0 (Rev. 1)
* Adds support for KU3P devices, and full example design support for all parts.
* Revision change in one or more subcores
IEEE 802.3bj RS-FEC (1.0)
* Version 1.0 (Rev. 5)
* Adds support for KU3P devices.
* Revision change in one or more subcores
ILA (Integrated Logic Analyzer) (6.1)
* Version 6.1 (Rev. 1)
* Revision change in one or more subcores
IOModule (3.0)
* Version 3.0 (Rev. 5)
* Provided register information for all registers, including description and bit field definitions
Image Enhancement (8.0)
* Version 8.0 (Rev. 10)
* Revision change in one or more subcores
Interlaken (1.10)
* Version 1.10
* Retransmission enabled in GUI for UltraScale+ devices
* Revision change in one or more subcores
Interleaver/De-interleaver (8.0)
* Version 8.0 (Rev. 9)
* No changes
JESD204 (7.0)
* Version 7.0 (Rev. 1)
* Set default value of gt_rxlpmen to 1 when Transceiver Debug is not enabled
* Improved reset handshaking logic between JESD204 and JESD204 PHY
* Revision change in one or more subcores
JESD204 PHY (3.1)
* Version 3.1 (Rev. 1)
* QPLLs are powered down by default when using CPLL only configurations to reduce power consumption
* Fixed issue where gt_rxlpmen was being set to 0 when Transceiver debug ports or the AXI4-Lite interface were enabled
* Set default value of gt_txdiffctrl to 0x1000 when AXI4-Lite Interface is enabled
* Revision change in one or more subcores
JTAG to AXI Master (1.1)
* Version 1.1 (Rev. 3)
* Revision change in one or more subcores
LMB BRAM Controller (4.0)
* Version 4.0 (Rev. 9)
* Provided register information for all registers, including description and bit field definitions
LTE DL Channel Encoder (3.0)
* Version 3.0 (Rev. 10)
* No changes
LTE Fast Fourier Transform (2.0)
* Version 2.0 (Rev. 11)
* No changes
LTE PUCCH Receiver (2.0)
* Version 2.0 (Rev. 10)
* No changes
LTE RACH Detector (2.0)
* Version 2.0 (Rev. 10)
* No changes
LTE UL Channel Decoder (4.0)
* Version 4.0 (Rev. 10)
* No changes
Local Memory Bus (LMB) 1.0 (3.0)
* Version 3.0 (Rev. 8)
* No changes
MIPI CSI-2 Rx Controller (1.0)
* Version 1.0 (Rev. 3)
* Revision change in one or more subcores
MIPI CSI-2 Rx Subsystem (2.0)
* Version 2.0 (Rev. 1)
* AXI IIC Instance FREQ_KHZ setting corrected to 400Khz
* Revision change in one or more subcores
MIPI D-PHY (2.0)
* Version 2.0 (Rev. 1)
* Fixed HS RX TIMEOUT parameter propagation for 3-lane D-PHY RX configuration
* Corrected the clkoutphy connection in D-PHY RX configuration
* Revision change in one or more subcores
MIPI DSI Tx Controller (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
MIPI DSI Tx Subsystem (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
Mailbox (2.1)
* Version 2.1 (Rev. 6)
* Provided register information for all registers, including description and bit field definitions
* Revision change in one or more subcores
Memory Helper Core (1.2)
* Version 1.2 (Rev. 1)
* Support for Vivado 2016.2
Memory Interface Generator (MIG 7 Series) (4.0)
* Version 4.0
* Updated the Maximum supported Frequency values as per the DS 181, DS 182, DS183, DS187 and DS191.
MicroBlaze (9.6)
* Version 9.6 (Rev. 1)
* Added AXI bus interface property HAS_BURST
MicroBlaze Debug Module (MDM) (3.2)
* Version 3.2 (Rev. 6)
* Provided register information for all registers, including description and bit field definitions
* Added AXI bus master interface property HAS_BURST
* Revision change in one or more subcores
MicroBlaze MCS (3.0)
* Version 3.0 (Rev. 1)
* Revision change in one or more subcores
Multiplier (12.0)
* Version 12.0 (Rev. 11)
* No changes
Multiply Adder (3.0)
* Version 3.0 (Rev. 9)
* No changes
Mutex (2.1)
* Version 2.1 (Rev. 7)
* Provided register information for all registers, including description and bit field definitions
PCIe PHY IP (1.0)
* Version 1.0 (Rev. 1)
* Added support for UltraScale devices xcku040-ffva1156 and xcvu440-flga2892.
* Added the PLL selection option for UltraScale+ devices in Gen2 speed.
* Fixed the core_clk issue for UltraScale+ devices.
* L0s fix for UltraScale+ devices.
* Updated GT related parameters.
* Revision change in one or more subcores
Partial Reconfiguration Controller (1.0)
* Version 1.0 (Rev. 4)
* Revision change in one or more subcores
Partial Reconfiguration Decoupler (1.0)
* Version 1.0 (Rev. 2)
* No changes
Peak Cancellation Crest Factor Reduction (6.0)
* Version 6.0 (Rev. 4)
* No changes
Processor System Reset (5.0)
* Version 5.0 (Rev. 9)
* No changes
QDRII+ SRAM (MIG) (1.2)
* Version 1.2 (Rev. 1)
* Support for Vivado 2016.2
* Revision change in one or more subcores
QDRIV SRAM (MIG) (1.1)
* Version 1.1 (Rev. 1)
* Updated for 2016.2 Vivado.
* Revision change in one or more subcores
QDRIV SRAM PHY IP (1.1)
* Version 1.1 (Rev. 2)
* Support for Vivado 2016.2
* Revision change in one or more subcores
QSGMII (3.3)
* Version 3.3 (Rev. 5)
* Bugfix for extra port required by GTWizard for older UltraScale devices which used calibration logic.
* Revision change in one or more subcores
RAM-based Shift Register (12.0)
* Version 12.0 (Rev. 9)
* No changes
RGB to YCrCb Color-Space Converter (7.1)
* Version 7.1 (Rev. 8)
* Revision change in one or more subcores
RLDRAM3 (MIG) (1.2)
* Version 1.2 (Rev. 1)
* Updated for 2016.2
* Revision change in one or more subcores
RXAUI (4.3)
* Version 4.3 (Rev. 5)
* Assigned 156.25 MHz value to FREQ_HZ bus parameter for refclk_out port
* Revision change in one or more subcores
Reed-Solomon Decoder (9.0)
* Version 9.0 (Rev. 11)
* No changes
Reed-Solomon Encoder (9.0)
* Version 9.0 (Rev. 10)
* No changes
S/PDIF (2.0)
* Version 2.0 (Rev. 12)
* Revision change in one or more subcores
SC EXIT (1.0)
* Version 1.0 (Rev. 1)
* Update to support improved metadata operation in Vivado IP Integrator
* Remove max_fanout attributes where no longer needed.
* Fixed read burst corruption when converting burst-to-singles to AXI4Lite slave and converting data-width.
* Revision change in one or more subcores
SC MMU (1.0)
* Version 1.0 (Rev. 1)
* Always reject FIXED transactions.
* Added SUPPORTS_WRAP parameter to optionally reject WRAP transactions.
* Revision change in one or more subcores
SC SI_CONVERTER (1.0)
* Version 1.0 (Rev. 1)
* Remove max_fanout attributes where no longer needed.
* Revision change in one or more subcores
SC SPLITTER (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
SC TRANSACTION_REGULATOR (1.0)
* Version 1.0 (Rev. 1)
* Fixed corner-case counter overflow: S_ID_WIDTH=0, SEP_ROUTE_WIDTH>0, NUM_OUTSTANDING>63.
* Revision change in one or more subcores
SMPTE 2022-1/2 Video over IP Receiver (2.0)
* Version 2.0 (Rev. 6)
* Revision change in one or more subcores
SMPTE 2022-1/2 Video over IP Transmitter (2.0)
* Version 2.0 (Rev. 6)
* Revision change in one or more subcores
SMPTE SD/HD/3G-SDI (3.0)
* Version 3.0 (Rev. 7)
* No changes
SMPTE ST 2059 (1.0)
* Version 1.0
* No changes
SMPTE UHD-SDI (1.0)
* Version 1.0 (Rev. 2)
* No changes
SMPTE2022-5/6 Video over IP Receiver (5.0)
* Version 5.0 (Rev. 5)
* Fixed high fanout in reset logic
* Revision change in one or more subcores
SMPTE2022-5/6 Video over IP Transmitter (4.0)
* Version 4.0 (Rev. 7)
* Fixed high fanout in reset logic
* Revision change in one or more subcores
SPI-4.2 (13.0)
* Version 13.0 (Rev. 8)
* No changes
ST2022-56 De-Packetizer (1.0)
* Version 1.0 (Rev. 1)
* core update for Vivado tool compatibility
ST2022-56 Packetizer (1.0)
* Version 1.0 (Rev. 1)
* core update for Vivado tool compatibility
SelectIO Interface Wizard (5.1)
* Version 5.1 (Rev. 7)
* No changes
Serial RapidIO Gen2 (4.0)
* Version 4.0 (Rev. 4)
* Revision change in one or more subcores
SmartConnect AXI2SC Bridge (1.0)
* Version 1.0 (Rev. 1)
* Update documentation
* Revision change in one or more subcores
SmartConnect Node (1.0)
* Version 1.0 (Rev. 1)
* Remove max_fanout attributes where no longer needed.
* Revision change in one or more subcores
SmartConnect SC2AXI Bridge (1.0)
* Version 1.0 (Rev. 1)
* Update documentation
* Revision change in one or more subcores
SmartConnect Switchboard (1.0)
* Version 1.0 (Rev. 1)
* Timing updates and RTL topology changes.
* Revision change in one or more subcores
Soft Error Mitigation (4.1)
* Version 4.1 (Rev. 6)
* Removed the workaround in 2016.1_AR67055 as the Vivado IP generation issue is fixed
System Cache (3.1)
* Version 3.1 (Rev. 4)
* Added AXI master bus interface property HAS_BURST
System Management Wizard (1.3)
* Version 1.3 (Rev. 1)
* HD banks have been added for monitoring, in UltraScale+ devices.
Timer Sync 1588 (1.2)
* Version 1.2 (Rev. 3)
* No changes
Tri Mode Ethernet MAC (9.0)
* Version 9.0 (Rev. 5)
* Revision change in one or more subcores
UltraScale 100G Ethernet Subsystem (1.10)
* Version 1.10
* Updated the trans debug module with read modify write feature for DRP registers for runtime switch
* Added support for xqku095 -1M devices
* Revision change in one or more subcores
UltraScale FPGA Gen3 Integrated Block for PCI Express (4.2)
* Version 4.2 (Rev. 1)
* Updated the Tandem with Field Updates example design scripts to handle IP core containers where the output products were not generated.
* Simplify falling edge receiver detect DRP logic
* Added logic to fix an issue in the core where the core left shifts the values of MSIX_CAP_TABLE_OFFSET and MSIX_CAP_PBA_OFFSET parameters for PF0,PF1, VF0-VF5 by 3 bits. The fix right shifts the values by 3 bits so that the implemented value in hardware is same as the one programed during the core configuration (Xilinx Answer 67111).
* Added support for defense grade Kintex UltraScale device xqku115
* Modified the insertion loss profile parameter to provide three options Chip-to-Chip(5db), Add-in_Card(15db) and Backplane(20db). Core operates in LPM mode for the values < 15db and DFE mode for the values >= 15db.
* Fixed GT DRP Clock Frequency for 125MHz and 250MHz Refclk Frequency
* Revision change in one or more subcores
UltraScale FPGAs Transceivers Wizard (1.6)
* Version 1.6 (Rev. 3)
* Improved performance and functionality of UltraScale+ GTY serial transceivers via parameter updates
* Improved reliability of UltraScale+ GTH and GTY transceivers via CPLL calibration block addition optionally
* Fixed a bug in the customization GUI that prevented selection of a legal user data width when targeting maximum line rate for some devices
* Revision change in one or more subcores
UltraScale Soft Error Mitigation (3.1)
* Version 3.1 (Rev. 1)
* Address timing issues on status_heartbeat in example design described in AR 66905
* Add support for xqku115 device
UltraScale+ 100G Ethernet Subsystem (1.0)
* Version 1.0 (Rev. 1)
* Updated the trans debug module with new GT DRP registers for runtime switch as per 2016.2
* Revision change in one or more subcores
UltraScale+ PCI Express Integrated Block (1.1)
* Version 1.1 (Rev. 1)
* Updated MSI-X CAP and NEXTPTR values.
* Added GT Settings tab for Insertion loss adjustment.
* Receiver detect drp module is replaced by receiver detect rxtermination module.
* Fixed GUI typo for BAR-5 and Exp ROM values.
* QPLL1 support is added for Gen2 (5.0 Gbps) speed along with CPLL. QPLL1 is default.
* Fixed I/O bank names in quad selection mode for xcvu9p-flga2104/flgb2104/flgc2104 and flga2577.
* Revision change in one or more subcores
VIO (Virtual Input/Output) (3.0)
* Version 3.0 (Rev. 12)
* Re customization issue fixed
* Revision change in one or more subcores
Video AXI4S Remapper (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
Video Deinterlacer (4.0)
* Version 4.0 (Rev. 10)
* No changes
Video In to AXI4-Stream (4.0)
* Version 4.0 (Rev. 3)
* Revision change in one or more subcores
Video Mixer (1.0)
* Version 1.0 (Rev. 1)
* Revision change in one or more subcores
Video On Screen Display (6.0)
* Version 6.0 (Rev. 11)
* Revision change in one or more subcores
Video PHY Controller (2.0)
* Version 2.0 (Rev. 2)
* DP protocol support added for GTHE4
* Revision change in one or more subcores
Video Processing Subsystem (2.0)
* Version 2.0 (Rev. 1)
* Revision change in one or more subcores
Video Scaler (8.1)
* Version 8.1 (Rev. 9)
* Revision change in one or more subcores
Video Test Pattern Generator (7.0)
* Version 7.0 (Rev. 3)
* Revision change in one or more subcores
Video Timing Controller (6.1)
* Version 6.1 (Rev. 8)
* Revision change in one or more subcores
Video over IP FEC Receiver (2.0)
* Version 2.0 (Rev. 1)
* Revision change in one or more subcores
Video over IP FEC Transmitter (2.0)
* Version 2.0 (Rev. 1)
* Revision change in one or more subcores
Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.2)
* Version 4.2 (Rev. 1)
* Added logic to right shift the values of the MSIX_CAP_TABLE_OFFSET and MSIX_CAP_PBA_OFFSET parameters for PF0,PF1,VF0-VF5 by 3 bits. The core left shifts the offset values by 3 bits and thus the final value is same as the programed value (Xilinx Answer 67111)
* Updated GT QPLL COMMON_CFG parameter
* Revision change in one or more subcores
Viterbi Decoder (9.1)
* Version 9.1 (Rev. 6)
* No changes
XADC Wizard (3.3)
* Version 3.3
* No changes
XAUI (12.2)
* Version 12.2 (Rev. 5)
* Revision change in one or more subcores
YCrCb to RGB Color-Space Converter (7.1)
* Version 7.1 (Rev. 8)
* Revision change in one or more subcores
ZYNQ UltraScale+ MPSoC (1.2)
* Version 1.2
* PCW GUI:
* 1) Clk & Ctl signals for Trace are not shown in GUI when trace width is selected as 16. This is fixed.
* 2) DP Aux ports are required for proper functionality of DisplayPort. Hence Aux is enabled when Display Port is selected.
* 3) MPSoC allows the option to route DPAUX through MIO. This has been enabled in 2016.2.
* Note that for ZU9 ES1 devices, it's recommended to not use the MIO option for DP Aux.
* 4) DRC enabled for clocking of GEM interfaces to allow only the divisor values which are generating correct frequencies as requested for GEM to work. The divisor values generated might not be scalable to frequencies other than the requested frequency. For Example, if the requested frequency is 25MHz then the divisor values can be generated to support 25MHz and 2.5MHz, but might not generate 125MHz.
* PCW Output: Support added for LPDDR3 in PCW
* IP:
* 1) Inverter has been added for interface signal with in the PS HDL wrapper for multiple tri-state based peripherals. This includes SPI, I2C, SDIO, MDIO for Ethernet and GPIO interfaces. As a result, all of the interfaces with _t_n ports are optional and not part of standard interface definition. New ports with _t are added to the interfaces. On upgrade from prior releases, _t_n ports will be used by default. It is the user's responsibility to update the connections. For all new designs starting in 2016.2, _t_n ports will not be available.
* 2) DP_Video_ref_clk and DP_Audio_ref_clk are brought out in the Zynq UltraScale+ MPSoC wrapper file.
* 3) Updates to support Clk & Ctl signals for Trace when width is > 16. Added HDL parameter as C_Trace_Data_Width
* 4) Other bug fixes.
ZYNQ7 Processing System (5.5)
* Version 5.5 (Rev. 3)
* No changes
ZYNQ7 Processing System BFM (2.0)
* Version 2.0 (Rev. 5)
* No changes
axi_sg (4.1)
* Version 4.1 (Rev. 3)
* Revision change in one or more subcores
interrupt_controller (3.1)
* Version 3.1 (Rev. 4)
* Revision change in one or more subcores
lib_bmg (1.0)
* Version 1.0 (Rev. 5)
* Revision change in one or more subcores
lib_cdc (1.0)
* Version 1.0 (Rev. 2)
* No changes
lib_fifo (1.0)
* Version 1.0 (Rev. 5)
* Revision change in one or more subcores
lib_pkg (1.0)
* Version 1.0 (Rev. 2)
* No changes
lib_srl_fifo (1.0)
* Version 1.0 (Rev. 2)
* No changes
| AR# 67345 | |
|---|---|
| 日期 | 06/21/2016 |
| 状态 | Active |
| Type | 版本说明 |
| Tools | |