When using the MIPI CSI-2 RX Subsystem v4.1 (rev.5) generated in Vivado 2019.2, an issue can occur where several lines per frame are not generated by the MIPI CSI-2 RX Subsystem when the sensor/TX is operating in non-continuous clock mode.
The IP works without issues in continuous clock mode.
The MIPI CSI-2 RX core (and MIPI D-PHY RX IP) registers do not show any errors during the issue, but if an ILA is inserted on the AXI4 stream bus at MIPI CSI-2 RX core output, the total line count might be less than expected.
This issue occurs in the Vivado 2019.2 generated LogiCORE MIPI CSI-2 RX Subsystem v4.1.
This issue will be fixed in Vivado 2020.1. The issue does not appear in versions prior to the 2019.2 release.
Vivado 2019.2 - Users can download the MIPI CSI-2 RX Subsystem patch from (Xilinx Answer 73100) to work around this issue.
It is recommended to update to the latest version of the IP.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 65242 | MIPI CSI-2 Receiver Subsystem - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions | N/A | N/A |