2. 技术支持
  3. AR# 7158: FPGA Express - VHDL Error: "Range 'U' to 'X' (or 'Z' to '-') not covered by choices. (VSS-838)"
  4. AR# 71582: 2018.2 LogiCORE IP MIPI D-PHY v4.1 (rev.1) MIPI CSI-2 RX Subsystem v3.0 (rev.3) - MIPI D-PHY RX or MIPI CSI-2 RX Subsystem reporting packet corruptions at higher line-rates

AR# 71582

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2018.2 LogiCORE IP MIPI D-PHY v4.1 (rev.1) MIPI CSI-2 RX Subsystem v3.0 (rev.3) - MIPI D-PHY RX or MIPI CSI-2 RX Subsystem reporting packet corruptions at higher line-rates

描述

When the MIPI D-PHY or MIPI CSI-2 RX Subsystems IPs are used in slave mode, processed packets received from the sensor report intermittent data corruptions at higher line-rates (for example, 1500Mbps).

This occurs for designs that do not have I/O termination.

解决方案

This issue occurs in the LogiCORE MIPI D-PHY RX and MIPI CSI-2 RX subsystem generated in Vivado 2018.2 and previous versions.

Internal termination of I/Os can be enabled using the below xdc constraints:

UltraScale+ devices:

set_property DIFF_TERM_ADV TERM_100 [get_ports <clk_rxp/n>] 
set_property DIFF_TERM_ADV TERM_100 [get_ports <data_rxp[*]/n[*]>]

7 Series devices:

set_property DIFF_TERM TRUE [get_ports <clk_rxp/n>] 
set_property DIFF_TERM TRUE [get_ports <data_rxp[*]/n[*]>

I/O termination is enabled by default in MIPI D-PHY RX and MIPI CSI-2 RX subsystems generated in the Vivado 2018.3 release.

AR# 71582
日期 01/21/2019
状态 Active
Type 综合文章
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