This answer record contains the Release Notes and Known Issues for the DDR3 UltraScale and UltraScale+ cores and includes the following:
This Release Notes and Known Issues Answer Record is for the programmable logic DDR3+ IP core supported in UltraScale and UltraScale+ based devices.
DDR3 IP Page
https://www.xilinx.com/products/intellectual-property/ddr3.html
Xilinx Forums:
Please seek technical support via the Memory Interfaces Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
General Information
Supported devices can be found in the following locations:
For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado tools.
Table 1 correlates the core version to the first Vivado design tools release version in which it was included.
Table 1: Version
| DDR3 Version | Vivado Tools Version |
| v1.4 (Rev. 10) | 2020.2 |
| v1.4 (Rev. 9) | 2020.1 |
| v1.4 (Rev. 8) | 2019.2 |
| v1.4 (Rev. 7) | 2019.1 |
| v1.4 (Rev. 6) | 2018.3 |
| v1.4 (Rev. 5) | 2018.2 |
| v1.4 (Rev. 4) | 2018.1 |
| v1.4 (Rev. 3) | 2017.4 |
| v1.4 (Rev. 2) | 2017.3 |
| v1.4 (Rev. 1) | 2017.2 |
| v1.4 | 2017.1 |
| v1.3 (Rev. 1) | 2016.4 |
| v1.3 | 2016.3 |
| v1.2 (Rev. 1) | 2016.2 |
| v1.2 | 2016.1 |
| v1.1 | 2015.4 |
| v1.0 | 2015.3 |
| v7.1 | 2015.2 |
| v7.0 | 2015.1 |
| v6.1 | 2014.4 |
| v6.0 | 2014.3 |
| v5.0 (Rev. 1) | 2014.2 |
| v5.0 | 2014.1 |
For a complete list of supported DDR3 memory devices refer to the memory_device_support_ddr3.xlsx attachment found at the bottom of this Answer Record.
For the latest info on what is new for Vivado, including supported operating systems and IP release notes, see (UG973).
Known and Resolved Issues
Table 2 provides the known and resolved issues for the UltraScale family DDR3 IP.
Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Table 2: Known and Resolved Issues
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 76121) | UltraScale/UltraScale+ and Zynq MPSoC DDR Memory Interface IP - PCB Simulation Support | NAB | NAB |
| (Xilinx Answer 73715) | UltraScale/UltraScale+ DDR3/DDR4 IP - Locked IPs using Self-Refresh with RDIMMs Must be Upgraded to Vivado 2020.1 or Later when Brought into Vivado 2020.1 and Later | v1.4 (Rev. 9) | NF |
| (Xilinx Answer 73714) | UltraScale/UltraScale+ Memory IP - Locked IPs from Earlier Versions of Vivado when Brought in to 2020.1 or Later Will Encounter Errors During Implementation or in Hardware | v1.4 (Rev. 9) | NF |
| (Xilinx Answer 73461) | UltraScale/UltraScale+ DDR3/DDR4 IP - Implemented design shows Memdata errors due to improperly or nonexistent instantiated BRAM and will not calibrate | v2.2 (Rev. 6) | v2.2 (Rev. 10) |
| (Xilinx Answer 73068) | Design Advisory for UltraScale/UltraScale+ DDR4/DDR3 IP - Memory IP Timing Exceptions May Manifest as Post Calibration Data Errors or DQS Gate Tracking Errors in Hardware | v1.3 (Rev. 1) | v1.4 (Rev. 9) |
| (Xilinx Answer 73052) | UltraScale/UltraScale+ DDR3/DDR4 IP - [Mig 66-119] PHY Core Regeneration and Stitching Failed | v1.0 | NF |
| (Xilinx Answer 72789) | UltraScale/UltraScale+ DDR3/DDR4 IP - Usage Guidelines for Multiple High Frequency Save/Restore Cycles | v1.3 | NF |
| (Xilinx Answer 72582) | UltraScale Memory IP - Space Grade Kintex UltraScale XQRKU060 Device Byte Planner Errors or MIG 66-99 Error in Bank 46 or Bank 25 | v2.2 (Rev. 7) | v1.4 (Rev. 9) |
| (Xilinx Answer 71531) | UltraScale/UltraScale+ DDR4 DDR3 Post Save Restore ECC errors multi-rank only | v2.2(Rev 5) | v1.4 (Rev. 6) |
| (Xilinx Answer 69071) | UltraScale/UltraScale+ DDR4/DDR3 IP - Simulations using UNISIM Models in NCSIM or using the ncinitialize Switch Gives Unexpected Results | v1.3 (Rev. 1) | NF |
| (Xilinx Answer 67956) | UltraScale/UltraScale+ DDR4/DDR3 - Supported configurations for Self Refresh and Save/Restore | v1.3 | v1.4 |
| (Xilinx Answer 66927) | UltraScale DDR4/DDR3 - BFM simulations have errors when using Self Refresh and Self Restore options | v1.3 | v1.3 (Rev. 1) |
| (Xilinx Answer 67544) | UltraScale DDR4/DDR3 - Tactical Patch - Data errors seen at user interface when using Normal Ordering Error | v1.2 | v1.3 |
| (Xilinx Answer 67891) | UltraScale DDR4/DDR3 - Ping-Pong PHY behavioral simulations fail with data errors when using BFM simulation mode | v1.2 (Rev. 1) | v1.3 |
| (Xilinx Answer 67455) | UltraScale DDR3/DDR4 - Tactical Patch - ECC signals are missing from the User Interface when ECC is enabled without AXI | v1.2 (Rev. 1) | v1.3 |
| (Xilinx Answer 66937) | UltraScale/UltraScale+ DDR4 and DDR3 IP - UNISIM simulations fail when using Self Refresh and Self Restore options | v1.2 | NAB |
| (Xilinx Answer 65083) | UltraScale+ MPSoC DDR4/DDR3 - No DIMM support for XCZU2EG and XCZU3EG devices with the SBVA484 package | v1.0 | v1.2 (Rev. 1) |
| (Xilinx Answer 66794) | UltraScale DDR3 - Write errors may be seen in dual rank or dual slot configurations in Vivado 2015.3 or 2015.4 due to Dynamic ODT settings | v1.0 | v1.2 |
| (Xilinx Answer 66560) | UltraScale/UltraScale+ DDR3 and DDR4 IP - IP Generation Fails when Custom Part CSV File is Loaded for Twin Die Component | v1.1 | v2.0 |
| (Xilinx Answer 65950) | UltraScale DDR4/DDR3 - Synplify PRO Synplify Pro Black Box Testing designs can fail in calibration | v1.0 | v1.2 |
| (Xilinx Answer 65421) | UltraScale DDR3 - tIS memory model violations on ADDR and BA occur when simulating DDR3 example_tb testbench | v5.0 | v1.2 |
| (Xilinx Answer 65493) | UltraScale DDR4/DDR3 - IP generation fails for configurations requiring more than 3 contiguous banks when targeting FGPA devices with half banks in between full banks | v1.0 | v1.1 |
| (Xilinx Answer 65790) | UltraScale DDR4/DDR3 - Tactical Patch - when using a Custom Memory part some timing parameters are not updated correctly | v1.0 | v1.1 |
| (Xilinx Answer 65652) | UltraScale DDR3/DDR4 - AXI enabled designs incorrectly have data mask tied to GND during Read-Modify-Write commands | v1.0 | v1.1 |
| (Xilinx Answer 65372) | UltraScale DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulator | v1.0 | v1.2 |
| (Xilinx Answer 64856) | Design Advisory for UltraScale DDR4/DDR3 - PCB pull-down required on the DDR3 RESET# pin and on the DDR4 RESET_N pin to maintain logic low during memory initialization | v5.0 | v7.1 |
| (Xilinx Answer 62086) | UltraScale DDR4/DDR3 - Performance Traffic Generator only works with "ROW COLUMN BANK" Address mapping | v5.0 (Rev. 1) | v1.2 |
| (Xilinx Answer 65261) | UltraScale DDR4/DDR3 - Tactical Patch - Dynamic DCI does not work for some devices | v7.1 | v1.0 |
| (Xilinx Answer 64775) | UltraScale DDR3 - tZQinit violations seen during DDR3 simulations | v7.1 | v1.0 |
| (Xilinx Answer 64773) | UltraScale DDR4/DDR3 - customization GUI shows incorrect Enable Chip Select Pin option when recustomizing IP | v7.0 | v1.0 |
| (Xilinx Answer 63787) | UltraScale DDR3 - ERRORs in simulation are seen when using the Micron memory model for sg125 speed grade with CAS Latency = 9 and CAS Write Latency = 7 | v7.0 | v1.0 |
| (Xilinx Answer 63852) | UltraScale DDR3 - Use of HR banks requires update of the output_impedance of all ports using reset_property command | v7.0 | NAB |
| (Xilinx Answer 64655) | UltraScale DDR3 - Tactical Patch - IP generation incorrectly enables address mirroring for dual rank DDR3 RDIMMs | v7.0 | v7.1 |
| (Xilinx Answer 64010) | UltraScale DDR4/DDR3 - memory controller can hang when in "Strict" mode | v7.0 | v7.1 |
| (Xilinx Answer 64146) | UltraScale DDR3 - simulation warnings for 16Gb and 8Gb DDR3 TwinDie parts | v7.0 | v7.1 |
| (Xilinx Answer 64063) | UltraScale DDR4/DDR3 - DIMM tool tip incorrectly lists the density for the base component part | v7.0 | v7.1 |
| (Xilinx Answer 63789) | UltraScale DDR3 - (HR banks only) When targeting the top data rates supported for -2/-3 speed grades, it is required to target a memory device one speed grade faster than the target data rate | v7.0 | v7.1 |
| (Xilinx Answer 63261) | UltraScale/UltraScale+ DDR3/DDR4/QDRII+ - Multi-driver errors found during LINT check | v6.1 | v7.0 |
| (Xilinx Answer 63596) | UltraScale DDR4/DDR3/RLDRAM3 - HOLD violations might be seen when using 2014.4.1 | v6.1 | v7.0 |
| (Xilinx Answer 63240) | UltraScale DDR4/DDR3 - PHY Only Documentation - (PG150) includes incorrect usage of "rdDataEn" in relation to "per_rd_done" (periodic read operation) and "rmw_rd_done" (RMW Operation) | v6.1 | v7.0 |
| (Xilinx Answer 62930) | UltraScale DDR4/DDR3 -Tactical Patch - tCCD and tRTW violations can cause data errors in multi-rank and DDR4 x16 configurations | v6.1 | v7.0 |
| (Xilinx Answer 62776) | UltraScale DDR4/DDR3 - ECC fault injection does not work | v6.1 | v7.0 |
| (Xilinx Answer 60528) | UltraScale DDR4/DDR3 - Vivado may fail to generate output products with 64-bit data width | v5.0 | v7.0 |
| (Xilinx Answer 62321) | UltraScale DDR4/DDR3 - User Interface ports direction incorrect in instantiation template | v5.0 | v6.1 |
| (Xilinx Answer 62050) | UltraScale DDR4/DDR3 - Can reset_n be allocated to an I/O or does it have to be within a memory interface bank? | v5.0 | v6.1 |
| (Xilinx Answer 61909) | UltraScale DDR3/DDR4 - app_wdf_data format clarification | v6.0 | v6.1 |
| (Xilinx Answer 61901) | UltraScale DDR3/DDR4 - memory model violations observed during simulation | v5.0 (Rev. 1) | NAB |
| (Xilinx Answer 61129) | UltraScale DDR3 - "ERROR: tCK(avg) minimum violation" | v5.0 (Rev. 1) | v6.0 |
| (Xilinx Answer 61988) | UltraScale DDR4/DDR3 - Hold violations may be seen on a path clocked by riu_clk | v6.0 | v6.1 |
| (Xilinx Answer 59948) | UltraScale DDR4/DDR3 - Incorrect clock connection on dbg_hub which can have a negative timing impact. | v5.0 | v 5.0 (Rev. 1) |
Revision History:
| 04/18/2017 | Created Separate Answer Record for DDR3 |
| 06/12/2017 | Updated for 2017.2; Added (Xilinx Answer 68028), (Xilinx Answer 69291) |
| 06/22/2017 | Added (Xilinx Answer 69324) |
| 07/31/2017 | Updated debugging link to (Xilinx Answer 68937) |
| 09/18/2017 | Updated formatting and updated for 2017.3 |
| 11/29/2017 | Updated for 2017.4 |
| 03/13/2018 | Updated for 2018.1 |
| 09/20/2018 | Updated for 2018.3 |
| 05/02/2019 | Updated for 2019.1 |
| 09/19/2019 | Added (Xilinx Answer 72789) and (Xilinx Answer 72582), Updated for 2019.2 |
| 11/04/2019 | Added AR#69071 |
| 11/19/2019 | Added AR73052 |
| 03/26/2020 | Added DAAR 73068 |
| 05/27/2020 | Added AR73714; Added AR73715; Updated for 2020.1 |
| 01/08/2021 | Updated for 2020.2 |
| 02/05/2021 | Added (Xilinx Answer 73461) |
| 03/02/2021 | Added AR#76121 |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 58435 | MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions | N/A | N/A |