Version Found: v6.1
Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3, See (Xilinx Answer 69037) for RLDRAM3
MIG UltraScale designs might fail with HOLD violations when using the new speed file in 2014.4.1.
Failures can been seen with the following configurations:
DDR3/DDR4 (Data widths >= 64 bits)
RLDRAM3 (All data widths)
If one of the above configurations is being used in 2014.4.1 and HOLD violations are seen within the MIG IP then running "phys_opt_desgin" can resolve the issue.
Post-Place Phys Opt Design (phys_opt_design) can be enabled in the Project Settings under Implementation or can be run manually via the Tcl command "phys_opt_design".
If timing failures are still seen after running "phys_opt_design", check if the violations are the same as the ones identified in (Xilinx Answer 63698).
If not, please open a Service Request for additional assistance.
Revision History:
03/09/2015 - Initial Release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 63175 | Kintex UltraScale FPGA KCU105 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
| 69036 | UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues | N/A | N/A |
| 69037 | UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues | N/A | N/A |
| 69035 | UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 63698 | UltraScale Kintex FPGA 速度文件的设计咨询 — 使用 ILA 内核将显示可安全忽略的保持时序裕量违规 | N/A | N/A |
| AR# 63596 | |
|---|---|
| 日期 | 12/19/2017 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |
| IP | |