AR# 61988

描述

Version Found: DDR4 v6.0, DDR3 v6.0

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

Hold violations similar to the following have been seen in implementations of the MIG DDR4/3 core:

Slack (VIOLATED) :        -0.113ns  (arrival time - required time)
  Source:                 u_SN349_virtexuDDR3_vlog_867MHz_vivado/inst/u_ddr3_mem_intfc/u_ddr3_phy/u_ddr_mc_cal/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQOut_post_r_reg[52]/C
                            (rising edge-triggered cell FDRE clocked by riu_clk  {rise@0.000ns fall@4.608ns period=9.216ns})
  Destination:            u_SN349_virtexuDDR3_vlog_867MHz_vivado/inst/u_ddr3_mem_intfc/u_ddr3_phy/u_ddr_mc_cal/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQ_reg[564]/D
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@2.304ns period=4.608ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - riu_clk rise@0.000ns)
  Data Path Delay:        0.595ns  (logic 0.252ns (42.353%)  route 0.343ns (57.647%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        0.512ns (DCD - SCD - CPR)

解决方案

These hold violations are seen more commonly on SSIT devices but have also been seen on some monolithic implementations.

These hold violations are under investigation. 

Please open a Service Request if this violation is seen.

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