Version Found: DDR4 v7.0, DDR3 v7.0
Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3
If a MIG v7.0 IP generated in Vivado 2015.1 is moved to Vivado 2015.2 and not updated, an error similar to the following will occur during implementation:
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:mig_ddrx_phy:1.2 for cell mig_0_phy.
ERROR: [Mig 66-102] Regeneration failed
ERROR: [Mig 66-100] Phy core regeneration & stitching failed.
This will occur for all MIG interface types.
The info message will change to reflect the type of interface and the name of the IP instance.
These errors occur because the 2015.1 MIG/PHY IP is not available in the 2015.2 build.
The tactical IP patch provided with this answer record allows 2015.1 MIG IP to be implemented in 2015.2.
Then open Vivado 2015.2 and run implementation.
The 2015.1 MIG IP will now implement with no errors and will not require an upgrade to the 2015.2 MIG IP.
Note: This tactical patch is only compatible with the Vivado 2015.2 and MIG UltraScale v7.1 IP.
| 文件名 | 文件大小 | File Type |
|---|---|---|
| AR64887_Vivado_2015_2_preliminary_rev1.zip | 1 MB | ZIP |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 69036 | UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues | N/A | N/A |
| 69035 | UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues | N/A | N/A |
| AR# 64887 | |
|---|---|
| 日期 | 01/17/2018 |
| 状态 | Active |
| Type | 已知问题 |
| 器件 | |
| Tools | |
| IP | |