AR# 65261

描述

Version Found: DDR4 v7.1, DDR3 v7.1

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

The DDR4 and DDR3 SDRAM IP use Dynamic DCI which is designed to enable DCI for reads and disable DCI for writes.

For some devices, this feature is not available and is disabled in the IP. 

However, there are two devices that Dynamic DCI was not disabled in properly, which can cause hardware failures as a result of DCI not being used properly.

Below is a complete list of devices that do not have Dynamic DCI disabled properly:

• KU115 ES2
• VU440 ES2

解决方案

To ensure that DCI is enabled properly during reads, the USE_DYNAMIC_DCI parameter inside the DDR4 and DDR3 SDRAM IP should be set to "0".

This disables the Dynamic DCI feature and ensures that DCI is always enabled.

In order to resolve these issues, you must install the attached tactical IP patch.

To install the patch, navigate to the $XILINX_VIVADO/patches and extract the contents of "AR65261_vivado_2015_2_preliminary_rev1" to a directory starting with the name AR65261 (for example, C:\Xilinx\Vivado\2015.2\patches\AR65261)), then open Vivado 2015.2 and generate all of your MIG UltraScale IP.

Note: This tactical patch is only compatible with the Vivado 2015.2 and MIG UltraScale v7.1 IP.

Revision History:

08/27/2015 - Initial Release

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