AR# 67891

描述

Version Found: DDR4 v2.0 (Rev. 1), DDR3 v1.2 (Rev. 1)

Version Resolved: See (Xilinx Answer 69035) for DDR4 and (Xilinx Answer 69036) for DDR3.

Ping-Pong PHY simulations can fail when both Channels drive the CAS command in the same clock cycle but with different Slots (refer to (PG150) for more details on Ping-Pong PHY usage).

When this condition occurs, the data_in_valid signal does not assert/deassert correctly which results in read data errors.

解决方案

This is a problem with the Bus Functional Model (BFM) and can be worked around by using the UNISIM simulation mode under the "Advanced" tab of the IP GUI.

Revision History:

09/19/2016 - Initial Release

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