Version Found: DDR4 v2.2 (Rev. 5), DDR3 v1.4 (Rev. 5), RLDRAM3 v1.4 (Rev. 5)
Version Resolved: For DDR4 (Xilinx Answer 69035), For DDR3 (Xilinx Answer 69036), For RLDRAM3 (Xilinx Answer 69037)
If I target an FSVE1156 RFSoC package in Vivado 2018.2 and earlier releases, the tool allows a 64-bit SODIMM topology.
However, when the Output Products are generated, an error is produced.
In Vivado 2018.3, the FSVE1156 RFSoC package now limits All Memory IP to only have component topologies, as per package restrictions.
Revision History:
05/08/2019 - Initial Release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 69035 | UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues | N/A | N/A |
| 69036 | UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues | N/A | N/A |
| 69037 | UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues | N/A | N/A |