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  3. AR# 54480: LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools

AR# 54480

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LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools

描述

This answer record contains the Release Notes and Known Issues for the JESD204 LogiCORE IP and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2013.1 and newer tools.

Please reference XTP025 - IP Release Notes Guide for past known issue logs and ISE support information.

For Known Issues within JESD204 ISE Core Generator version, please visit (Xilinx Answer 44405), JESD204 LogiCORE IP - Release Notes and Known Issues.

JESD204 LogiCORE IP Page:

https://www.xilinx.com/content/xilinx/en/products/intellectual-property/ef-di-jesd204.html


Xilinx Forums:

Please seek technical support via the Networking and Connectivity Board. The Xilinx Forums are a great resource for technical support. 

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.

解决方案

General Information

Supported devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools. 


Alternatively, see the Change Log Answer Records:

 

Answer RecordTitle
(Xilinx Answer 71806)2018.3 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 71212)2018.2 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 70699)2018.1 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 70386)2017.4 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 69903)2017.3 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 69326)2017.2 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 69055)2017.1 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 68369)2016.4 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 68021)2016.3 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 67345)2016.2 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 66930)2016.1 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 66004)2015.4 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 65570)2015.3 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 65077)2015.2 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 64619)2015.1 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 63724)2014.4.1 Vivado IP Release Notes - All IP change Log Information
(Xilinx Answer 62882)2014.4 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 62144)2014.3 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 61087)2014.2 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 59986)2014.1 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 58670)2013.4 Vivado IP Release Notes - All IP Change Log Information
(Xilinx Answer 58605)2013.3 Vivado IP Release Notes - All IP Change Log Information

 

For any Transceiver related questions or issue, please see the table below.

Answer RecordTitle
(Xilinx Answer 41613)7 Series FPGAs GTX/GTH Transceivers - Known Issues and Answer Record List
(Xilinx Answer 57487)UltraScale FPGA Transceiver Wizard - Release Notes and Known Issues for Vivado 2013.4 and newer versions
(Xilinx Answer 62670)UltraScale FPGAs GTH Transceiver - Known Issues and Answer Record List
(Xilinx Answer 64440)UltraScale FPGA GTY Transceiver - Known Issues and Answer Record List
(Xilinx Answer 64838)Design Advisory for UltraScale FPGA Transceivers Wizard: GTH Production Updates in Vivado 2015.2


Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core VersionVivado Tools Version
v7.2 (Rev. 6)2019.1
v7.2 (Rev. 5)2018.3.1
v7.2 (Rev. 4)2018.3
v7.2 (Rev. 3)2018.2
v7.2 (Rev. 2)2018.1
v7.2 (Rev. 1)2017.4
v7.22017.3
v7.1 (Rev. 3)2017.2
v7,1 (Rev. 2)2017.1
v7.1 (Rev. 1)2016.4
v7.12016.3
v7.0 (Rev. 1)2016.2
v7.02016.1
v6.2 (Rev. 1)2015.4
v6.22015.3
v6.1 (Rev. 1)2015.2
v6.12015.1
v6.0 (Rev. 2)2014.4.1
v6.0 (Rev. 1)2014.4
v6.02014.3
v5.2 (Rev. 1)2014.2
v5.22014.1
v5.12013.4
v5.02013.3
v4.0 (Rev. 1)2013.2
v4.02013.1


General Guidance

The table below provides answer records for general guidance when using the JESD204B LogiCORE IP.

Answer RecordTitle
(Xilinx Answer 66143)IP JESD204 - Latency calculations checklist
(Xilinx Answer 66826)JESD204 - Reset pulse width information
(Xilinx Answer 67991)JESD204 - Information on rx_start_of_frame
(Xilinx Answer 69610)JESD204B - Can one instance of a JESD204B core be used with multiple ADCs or DACs?
(Xilinx Answer 71575)JESD204B - Guidance when using multiple JESD204 RX cores to connect to one or more ADC's


Known and Resolved Issues

The following table provides known issues for the JESD204 LogiCORE IP, starting with v4.0, initially released in Vivado 2013.1.

Note: The "Version Found" column lists the version the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 72355)JESD204 - 2019.1 - Architecture limitationsv7.2 (Rev. 6)
(Xilinx Answer 70144)JESD204 v7.2 and JESD204 PHY v4.0 - Patch update for JESD204 core in Vivado 2017.3 to enable GTY selection for XCZU19EG-FFVD1760 devicesv7.2 / v4.0v7.2 (Rev. 1) / v4.0 (Rev. 1)
(Xilinx Answer 69507)JESD204B (v7.0) - RXLPMEN values incorrect when shared logic in core is usedv7.0
(Xilinx Answer 69027)JESD204 - Single Lane JESD204 Transmit Example Design simulations timing out when using QuestaSim
(Xilinx Answer 69021)JESD204 - 2017.1 - UltraScale / UltraScale+ IBUFDS_GTE output instability
(Xilinx Answer 67354)JESD204 PHY - CPLLPD is not held high for at least 2us
(Xilinx Answer 67349)JESD204B v7.0 - TX Lane ID is incorrect in ILA sequence, resulting in possible Example Design simulation failurev7.0v7.1
(Xilinx Answer 67043)JESD204 v6.1, v6.2, v7.0 and JESD204 PHY v2.0, v3.0, v3.1 (2015.1, 2015.2, 2015.3, 2015.4, 2016.1) - Defaults to DFE Equalization mode
(Xilinx Answer 66575)JESD204 and JESD204 PHY - Multi-lane JESD interfaces and the rxencommaalign signal
(Xilinx Answer 65479)JESD204B - Single Lane JESD204 Transmit Example Design Simulations Timing Out When Using QuestaSim
(Xilinx Answer 64709)JESD204 v6.1 - Migrating from 2014.4 to 2015.1 - Achieving SYNCv6.1
(Xilinx Answer 64524)JESD204 v6.1 - Patch Update for JESD204 core in Vivado 2015.1v6.1v6.1 (Rev. 1)
(Xilinx Answer 63849)JESD204 v6.1 PG066 Product Guide - Table 2-14 and 2-15 contain typosv6.1v7.0
(Xilinx Answer 63345)JESD204 v6.0 PG066 Product Guide - Table 2-30 Error Reporting bits are swappedv6.0v6.1
(Xilinx Answer 62470)JESD204 v5.2 - CPLL Power Down not driven on startup if default rate line used in JESD204 v5.2 in 2014.2v5.2v6.0
(Xilinx Answer 61933)PG066 (v5.2) - Description of SYNC~ behavior in Figure 3-8 is incorrectv5.2v6.0
(Xilinx Answer 60387)UltraScale GT wrapper for multi-lane core has incorrect connections for DRPCLK v5.2v5.2
(Xilinx Answer 60386)v5.1 - upgrade to JESD204 v5.2 in Vivado 2014.1 fails for RX coresv5.1v5.2
(Xilinx Answer 59595) Vivado-Line Rate and Reference Clock change Procedure for JESD204 core in Virtex-7 Devices for line rates where the RXOUT_DIV>1.v5.1v6.0
(Xilinx Answer 59040)Vivado Synthesis will produce errors indicating that ports do not exist in the transceiver wrapper. v5.1v5.2
(Xilinx Answer 58747)RX TVALID not correctly asserted under certain conditionsv5.1v5.2
(Xilinx Answer 55503)Setting RX Lanes In Use to less than the value chosen during configuration causes RX Data Valid not to be asserted correctly v4.0v4.0 (Rev. 1)
(Xilinx Answer 55460)AXI4-Lite address decode incorrect for 8bit and 16bit writes to the RX Buffer Delay and Frames per Multiframe register v4.0v5.0
(Xilinx Answer 55857)Updated RX Termination settings for 7 Series GTP and GTHv4.0v5.0
(Xilinx Answer 56078)Updated RX Buffer settings for 7 Series FPGA GTX, GTP and GTH v4.0v5.0
(Xilinx Answer 56079)JESD204B - v4.0 - Updated procedure for replicating the GT Wrappers in Vivado Design Suite 2013.2v4.0v5.0



Revision History

05/13/2019Updated for 2019.1 release
12/13/2018Added (Xilinx Answer 71806); updated for 2018.3 release
10/11/2018
11/15/2017		Added (Xilinx Answer 71575)
Added (Xilinx Answer 70144)
10/10/2017Updated for 2017.3 release
10/08/2017Added (Xilinx Answer 69610)
11/04/2017Updated for 2017.1 release
03/14/2017Updated for 2016.3 and 2016.4
10/17/2016Added (Xilinx Answer 67354)
06/10/2016Added (Xilinx Answer 67345), (Xilinx Answer 67349)
05/11/2016Added (Xilinx Answer 67043), (Xilinx Answer 66930)
02/09/2016Added (Xilinx Answer 66575)
12/10/2015Added (Xilinx Answer 65570) and (Xilinx Answer 66004). Updated for 2015.4 release
08/26/2015Added (Xilinx Answer 64709) and (Xilinx Answer 65077). Updated for 2015.2 release
07/03/2015Added (Xilinx Answer 64838)
06/04/2015Updated for 2015.1 release. Added (Xilinx Answer 62670) and (Xilinx Answer (64440)
05/20/2015Updated for 2014.4.1 release. Added (Xilinx Answer 63724) and (Xilinx Answer 64524)
01/20/2015Updated for 2014.4 release. Added (Xilinx Answer 63345)
10/03/2014Updated for 2014.3 release
10/02/2014Entered Version Resolved for (Xilinx Answer 59595)
09/05/2014Updated for 2014.3 and added (Xilinx Answer 61933)
04/24/2014Added (Xilinx Answer 59595), (Xilinx Answer 60386), (Xilinx Answer 60387)
03/10/2014Added (Xilinx Answer 58671)
01/10/2014Added (Xilinx Answer 59040)
01/07/2014Added (Xilinx Answer 58747)
12/18/2013Updated for 2013.4
06/20/2013Added (Xilinx Answer 56078)
04/03/2013Initial Release

附件

文件名 文件大小 File Type
AR65533_Vivado_2015_2_preliminary_rev2.zip 367 KB ZIP

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
67698 JESD204 Solution Center - Top Issues and Frequently Asked Questions N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
55857 JESD204B v4.0 or earlier - Updated RX Termination settings for 7 Series FPGA GTP and GTH N/A N/A
55503 JESD204 V4.0 - Vivado - Setting Rx Lanes in use to less than the value chosen during configuration causes Rx Data Valid not to be asserted correctly N/A N/A
55460 JESD204 V4.0 - AXI4-Lite address decode incorrect for 8bit and 16bit writes to the Rx Buffer Delay and Frames per Multiframe register N/A N/A
56078 JESD204B v4.0 - Updated RX Buffer settings for 7 Series FPGA GTX, GTP and GTH N/A N/A
58089 LogiCORE IP JESD204B v5.0 - RX Register Address decide unintended offset for multi-lane cores greater than 2 lanes N/A N/A
58747 JESD204 v5.1 IP - 在某些条件下，未正确断言 Rx TVALID N/A N/A
60386 JESD204 v5.1 - upgrade to JESD204 v5.2 in Vivado 2014.1 fails for Rx cores N/A N/A
61933 PG066 (v5.2) - Description of SYNC~ behavior in Figure 3-8 is incorrect N/A N/A
58605 2013.3 Vivado IP Release Notes - All IP Change Log Information N/A N/A
58670 2013.4 Vivado IP Release Notes - All IP Change Log Information N/A N/A
59986 2014.1 Vivado IP Release Notes - All IP Change Log Information N/A N/A
61087 2014.2 Vivado IP 版本说明 - 所有 IP 变更信息 N/A N/A
59595 Vivado-Line Rate and Reference Clock change Procedure for JESD204 core in Virtex7 Devices for line rates where the RXOUT_DIV>1. N/A N/A
41613 7 Series FPGAs GTX/GTH Transceivers - Known Issues and Answer Record List N/A N/A
62470 JESD204 v5.2 - CPLL Power Down not driven on startup if default rate line used in JESD204 v5.2 in 2014.2 N/A N/A
59294 设计咨询 GT 向导 – CPLL 在 7 系列 GT 上电时产生功率尖峰 N/A N/A
63345 JESD204 v6.0 PG066 Product Guide - Table 2-30 Error Reporting bits are swapped N/A N/A
63849 JESD204 v6.1 (PG066) Product Guide - Table 2-14 and Table 2-15 contain typos N/A N/A
64445 JESD204 v6.1- Why do I see incorrectly aligned SYNC output on JESD Receiver? N/A N/A
64524 JESD204 v6.1 - Patch Update for JESD204 core in Vivado 2015.1 N/A N/A
62670 UltraScale FPGAs GTH Transceiver - Known Issues and Answer Record List N/A N/A
64440 UltraScale FPGA GTY Transceiver - Known Issues and Answer Record List N/A N/A
65479 JESD204B - Single Lane JESD204 Transmit Example Design Simulations Timing Out When Using QuestaSim N/A N/A
65570 2015.3 Vivado IP Release Notes - All IP Change Log Information N/A N/A
66004 2015.4 Vivado IP Release Notes - All IP Change Log Information Article N/A N/A
66575 JESD204 和 JESD204 PHY — JESD 接口和 rxencommaalign 信号 N/A N/A
66576 JESD204 - Clock stability N/A N/A
67043 JESD204 v6.1, v6.2, v7.0 and JESD204 PHY v2.0, v3.0, v3.1 (2015.1, 2015.2, 2015.3, 2015.4, 2016.1) - Defaults to DFE Equalisation mode N/A N/A
66930 2016.1 Vivado IP Release Notes - All IP Change Log Information Article N/A N/A
67354 JESD204 PHY - CPLLPD is not held high for at least 2us N/A N/A
69027 JESD204 - Single Lane JESD204 Transmit Example Design simulations timing out when using QuestaSim N/A N/A
69055 2017.1 Vivado IP Release Notes - All IP Change Log Information Article N/A N/A
69507 JESD204B (v7.0) - RXLPMEN values incorrect when shared logic in core is used N/A N/A
70144 JESD204 v7.2 and JESD204 PHY v4.0 - Patch update for JESD204 core in Vivado 2017.3 to enable GTY selection for XCZU19EG-FFVD1760 devices N/A N/A
71806 2018.3 Vivado IP Release Notes - All IP Change Log Information N/A N/A
72355 JESD204 - 2019.1 - Architecture limitations N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
44405 LogiCORE IP JESD204 - 发布说明和已知问题 N/A N/A
64838 UltraScale FPGA 收发器向导的设计咨询：Vivado 2015.2 中的 GTH 生产更新 N/A N/A
AR# 54480
日期 05/29/2019
状态 Active
Type 版本说明
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