AR# 66004

描述

This Answer Record contains a comprehensive list of IP changelog information from Vivado 2015.4 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

解决方案

(c) Copyright 2015 Xilinx, Inc. All rights reserved.

This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws.

DISCLAIMER
This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: 

(1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, OR FTNESS FOR ANY PARTICULAR PURPOSE; and

(2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability.

THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.

100G Ethernet (1.8)

* Version 1.8

* Kintex095 ffva1156 package support

* Support for Runtime Switchable case for CAUI-10 to 4 option as default option

* Virtex UltraScale -1H and -1HV devices support

* UltraScale plus device support for simulation only

* Revision change in one or more subcores

10G Ethernet MAC (15.0)

* Version 15.0 (Rev. 3)

* Removing support for UltraScale plus devices for this product line

10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)

* Version 6.0 (Rev. 3)

* Support for -1L speedgrade in UltraScale devices

* Fix for PRBS11 section of training sequence getting stuck at zero

* Removing support for UltraScale plus devices for this product line

* Revision change in one or more subcores

10G Ethernet Subsystem (3.0)

* Version 3.0 (Rev. 3)

* No Functional changes.

* Removing support for UltraScale plus devices for this product line

* Revision change in one or more subcores

10G/25G Ethernet Subsystem (1.1)

* Version 1.1

* Implementation failure fixes

* Virtexuplus family support added

* Revision change in one or more subcores

1G/2.5G Ethernet PCS/PMA or SGMII (15.1)

* Version 15.1 (Rev. 1)

* Updated Default Latency numbers of GTXE2 and GTHE2 transceivers.

* Removing Transceiver_type user parameter as its redundant and not user editable.

* Revision change in one or more subcores

32-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 7)

* No changes

3GPP LTE Channel Estimator (2.0)

* Version 2.0 (Rev. 10)

* Fixed unexpected latency issue recorded in AR65470

* Revision change in one or more subcores

3GPP LTE MIMO Decoder (3.0)

* Version 3.0 (Rev. 10)

* Revision change in one or more subcores

3GPP LTE MIMO Encoder (4.0)

* Version 4.0 (Rev. 9)

* Revision change in one or more subcores

3GPP Mixed Mode Turbo Decoder (2.0)

* Version 2.0 (Rev. 10)

* Revision change in one or more subcores

3GPP Turbo Encoder (5.0)

* Version 5.0 (Rev. 9)

* Revision change in one or more subcores

3GPPLTE Turbo Encoder (4.0)

* Version 4.0 (Rev. 9)

* Revision change in one or more subcores

64-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 7)

* No changes

7 Series FPGAs Transceivers Wizard (3.6)

* Version 3.6 (Rev. 1)

* Added support for new speedgrades of XQ7K325T and XQ7K410T devices

* Added support for new speedgrades of XQ7Z030, XQ7Z045 and XQ7Z100 devices

* Added support for new speedgrades of XQ7A050T, XQ7A100T and XQ7A200T devices

7 Series Integrated Block for PCI Express (3.2)

* Version 3.2 (Rev. 1)

* Fixed unresolved instances of sys_clk_gen used in pipe mode simulations. This module is now delivered in 'source' directory

AHB-Lite to AXI Bridge (3.0)

* Version 3.0 (Rev. 4)

* No changes

AXI 1G/2.5G Ethernet Subsystem (7.0)

* Version 7.0 (Rev. 3)

* No Functional changes.

* Revision change in one or more subcores

AXI AHBLite Bridge (3.0)

* Version 3.0 (Rev. 5)

* RTL fix to resolve corner case 1Kb splitting issue in read transaction at AHB Interface

* RTL fixes to resolve incorrect behavior on Read Data channel and Write Response channel at AXI Interface when interface is throttled

* Fixed RTL for AHB error propagation to AXI Interface in certain scenario (single write burst)

AXI APB Bridge (3.0)

* Version 3.0 (Rev. 4)

* No changes

AXI BFM Cores (5.0)

* Version 5.0 (Rev. 7)

* No changes

AXI BRAM Controller (4.0)

* Version 4.0 (Rev. 6)

* Revision change in one or more subcores

AXI Bridge for PCI Express Gen3 Subsystem (2.0)

* Version 2.0 (Rev. 1)

* Added support for ffva1156 package for xcku095 device

* Revision change in one or more subcores

AXI CAN (5.0)

* Version 5.0 (Rev. 10)

* Revision change in one or more subcores

AXI Central Direct Memory Access (4.1)

* Version 4.1 (Rev. 7)

* Revision change in one or more subcores

AXI Chip2Chip Bridge (4.2)

* Version 4.2 (Rev. 7)

* Example design update for Aurora drpaddr port width mismatch. No functional changes

* Revision change in one or more subcores

AXI Clock Converter (2.1)

* Version 2.1 (Rev. 6)

* Revision change in one or more subcores

AXI Crossbar (2.1)

* Version 2.1 (Rev. 8)

* Revision change in one or more subcores

AXI Data FIFO (2.1)

* Version 2.1 (Rev. 6)

* Revision change in one or more subcores

AXI Data Width Converter (2.1)

* Version 2.1 (Rev. 7)

* Revision change in one or more subcores

AXI DataMover (5.1)

* Version 5.1 (Rev. 9)

* Revision change in one or more subcores

AXI Direct Memory Access (7.1)

* Version 7.1 (Rev. 8)

* Revision change in one or more subcores

AXI EMC (3.0)

* Version 3.0 (Rev. 7)

* Corrected the IP level IOB constraints on Memory Interface Ports when STARTUP is enabled (Xilinx Answer 65523)

AXI EPC (2.0)

* Version 2.0 (Rev. 10)

* Example design constraint update. No functional changes.

AXI Ethernet Buffer (2.0)

* Version 2.0 (Rev. 10)

* Revision change in one or more subcores

AXI Ethernet Clocking (2.0)

* Version 2.0 (Rev. 2)

* No changes

AXI Ethernet Lite (3.0)

* Version 3.0 (Rev. 5)

* Revision change in one or more subcores

AXI GPIO (2.0)

* Version 2.0 (Rev. 9)

* Revision change in one or more subcores

AXI HWICAP (3.0)

* Version 3.0 (Rev. 11)

* Example design update. No functional changes.

* Revision change in one or more subcores

AXI IIC (2.0)

* Version 2.0 (Rev. 10)

* Revision change in one or more subcores

AXI Interconnect (2.1)

* Version 2.1 (Rev. 8)

* Revision change in one or more subcores

AXI Interrupt Controller (4.1)

* Version 4.1 (Rev. 5)

* No changes

AXI Lite IPIF (3.0)

* Version 3.0 (Rev. 3)

* No changes

AXI MMU (2.1)

* Version 2.1 (Rev. 5)

* Revision change in one or more subcores

AXI Master Burst (2.0)

* Version 2.0 (Rev. 7)

* No changes

AXI Memory Mapped To PCI Express (2.7)

* Version 2.7 (Rev. 1)

* Fixed intermittent MSI packet lost (Xilinx Answer 65647)

* Revision change in one or more subcores

AXI Memory Mapped to Stream Mapper (1.1)

* Version 1.1 (Rev. 6)

* Revision change in one or more subcores

AXI Performance Monitor (5.0)

* Version 5.0 (Rev. 9)

* Revision change in one or more subcores

AXI Protocol Checker (1.1)

* Version 1.1 (Rev. 8)

* Revision change in one or more subcores

AXI Protocol Converter (2.1)

* Version 2.1 (Rev. 7)

* Revision change in one or more subcores

AXI Quad SPI (3.2)

* Version 3.2 (Rev. 6)

* Fixed DRR overrun generation issue

* XIP mode slave select signal generation issue fixed

* Revision change in one or more subcores

AXI Register Slice (2.1)

* Version 2.1 (Rev. 7)

* Revision change in one or more subcores

AXI TFT Controller (2.0)

* Version 2.0 (Rev. 11)

* Revision change in one or more subcores

AXI Timebase Watchdog Timer (2.0)

* Version 2.0 (Rev. 8)

* No changes

AXI Timer (2.0)

* Version 2.0 (Rev. 8)

* No changes

AXI Traffic Generator (2.0)

* Version 2.0 (Rev. 8)

* Updated Internal parameter value that determines the transaction gap in static mode

* Revision change in one or more subcores

AXI UART16550 (2.0)

* Version 2.0 (Rev. 8)

* No changes

AXI USB2 Device (5.0)

* Version 5.0 (Rev. 8)

* Revision change in one or more subcores

AXI Uartlite (2.0)

* Version 2.0 (Rev. 10)

* No changes

AXI Video Direct Memory Access (6.2)

* Version 6.2 (Rev. 6)

* Revision change in one or more subcores

AXI Virtual FIFO Controller (2.0)

* Version 2.0 (Rev. 9)

* Revision change in one or more subcores

AXI-Stream FIFO (4.1)

* Version 4.1 (Rev. 4)

* Revision change in one or more subcores

AXI4-Stream Accelerator Adapter (2.1)

* Version 2.1 (Rev. 6)

* Revision change in one or more subcores

AXI4-Stream Broadcaster (1.1)

* Version 1.1 (Rev. 7)

* Revision change in one or more subcores

AXI4-Stream Clock Converter (1.1)

* Version 1.1 (Rev. 8)

* Revision change in one or more subcores

AXI4-Stream Combiner (1.1)

* Version 1.1 (Rev. 6)

* Revision change in one or more subcores

AXI4-Stream Data FIFO (1.1)

* Version 1.1 (Rev. 8)

* Revision change in one or more subcores

AXI4-Stream Data Width Converter (1.1)

* Version 1.1 (Rev. 6)

* Revision change in one or more subcores

AXI4-Stream Interconnect (2.1)

* Version 2.1 (Rev. 8)

* Revision change in one or more subcores

AXI4-Stream Protocol Checker (1.1)

* Version 1.1 (Rev. 7)

* Revision change in one or more subcores

AXI4-Stream Register Slice (1.1)

* Version 1.1 (Rev. 7)

* Revision change in one or more subcores

AXI4-Stream Subset Converter (1.1)

* Version 1.1 (Rev. 7)

* Revision change in one or more subcores

AXI4-Stream Switch (1.1)

* Version 1.1 (Rev. 7)

* Change IPXACT logical ports to uppercase

* Revision change in one or more subcores

AXI4-Stream to Video Out (4.0)

* Version 4.0 (Rev. 1)

* Revision change in one or more subcores

Accumulator (12.0)

* Version 12.0 (Rev. 8)

* Revision change in one or more subcores

Adder/Subtracter (12.0)

* Version 12.0 (Rev. 8)

* Bugfix for 47-bit unsigned adder targeting DSP Slice which gave array index error when synthesizing.

* Revision change in one or more subcores

Aurora 64B66B (11.0)

* Version 11.0 (Rev. 1)

* Added support for new speedgrades of XQ7K325T and XQ7K410T devices

* Added support for new speedgrades of XQ7Z030, XQ7Z045 and XQ7Z100 devices

* Revision change in one or more subcores

Aurora 8B10B (11.0)

* Version 11.0 (Rev. 3)

* Added support for new speedgrades of XQ7K325T and XQ7K410T devices

* Added support for new speedgrades of XQ7Z030, XQ7Z045 and XQ7Z100 devices

* Added support for new speedgrades of XQ7A050T, XQ7A100T and XQ7A200T devices

* Revision change in one or more subcores

Binary Counter (12.0)

* Version 12.0 (Rev. 8)

* Revision change in one or more subcores

Block Memory Generator (8.3)

* Version 8.3 (Rev. 1)

* Updated the IP to support the device package changes

CANFD (1.0)

* Version 1.0

* First Release of IP (beta)

* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

* Note that CAN FD IP user needs to buy Protocol License from Robert Bosch to before selling a device containing the CAN FD IP core

CIC Compiler (4.0)

* Version 4.0 (Rev. 9)

* Revision change in one or more subcores

CORDIC (6.0)

* Version 6.0 (Rev. 9)

* Revision change in one or more subcores

CPRI (8.5)

* Version 8.5 (Rev. 1)

* Updated the block sync state machine to the latest output by the 7 series transceiver wizard. Minor bug fix for 2015.3.

* Added new GTYE3 transceiver channel parameter updates. Minor upgrade.

* Added missing signals to the transceiver_debug & transceiver_monitor interfaces. Minor interface change.

* Tightened clock crossing constraints for UltraScale 12.16512Gbps capable cores. Bug fix for 2015.3.

* Added fix for Artix7 transceiver_monitor interface, receive ports had incorrect bus widths.

* Added support for new 7-series speed grades -1IL, -1ML, -2IL. New for 2015.4.

* Added fix for stat_speed output glitch for UltraScale 12.16512Gbps capable cores. Bug fix for 2015.3.

* Added fix for user DRP accesses. UltraScale and 7-series bug fix for 2015.3.

* Revision change in one or more subcores

Chroma Resampler (4.0)

* Version 4.0 (Rev. 7)

* No changes

Clocking Wizard (5.2)

* Version 5.2 (Rev. 1)

* Internal device family change, no functional changes

Color Correction Matrix (6.0)

* Version 6.0 (Rev. 8)

* No changes

Color Filter Array Interpolation (7.0)

* Version 7.0 (Rev. 7)

* No changes

Complex Multiplier (6.0)

* Version 6.0 (Rev. 10)

* Revision change in one or more subcores

Convolution Encoder (9.0)

* Version 9.0 (Rev. 9)

* Revision change in one or more subcores

DDR3 SDRAM (MIG) (1.1)

* Version 1.1

* Updated for 2015.4

* Resolved issues related to AXI enabled designs incorrectly having data mask tied to GND during Read-Modify-Write commands,  See (Xilinx Answer 65652) for details.

* Resolved issues related to  pblocks containing UltraScale Memory IP logic must be contained within the same clock region the memory I/O is located in.  See (Xilinx Answer 65370) for details.

* Resolved issues related to false DRC MIG-32

* Resolved issues related to sys_rst missing set_false_path constraint. See (Xilinx Answer 64188) for details.

* Revision change in one or more subcores

DDR4 SDRAM (MIG) (1.1)

* Version 1.1

* Updated for 2015.4

* Resolved issues related to AXI enabled designs incorrectly having data mask tied to GND during Read-Modify-Write commands,  See (Xilinx Answer 65652) for details.

* Resolved issues related to  pblocks containing UltraScale Memory IP logic must be contained within the same clock region the memory I/O is located in.  See (Xilinx Answer 65370) for details.

* Resolved issues related to false DRC MIG-32

* Resolved issues related to sys_rst missing set_false_path constraint. See (Xilinx Answer 64188) for details.

* Revision change in one or more subcores

DDS Compiler (6.0)

* Version 6.0 (Rev. 11)

* Revision change in one or more subcores

DMA Subsystem for PCI Express (PCIe) (1.0)

* Version 1.0 (Rev. 1)

* Added support for ffva1156 package for xcku095 device

* Revision change in one or more subcores

DSP48 Macro (3.0)

* Version 3.0 (Rev. 11)

* Revision change in one or more subcores

DUC/DDC Compiler (3.0)

* Version 3.0 (Rev. 9)

* Revision change in one or more subcores

Discrete Fourier Transform (4.0)

* Version 4.0 (Rev. 10)

* Revision change in one or more subcores

DisplayPort (6.1)

* Version 6.1 (Rev. 1)

* Added external AUX IO buffer support

* Updated the XDC of IP to improve run time

* Revision change in one or more subcores

DisplayPort RX Subsystem (1.0)

* Version 1.0

* Initial Release

* Displayport RX subsystem with 1/2/4 lanes

* AXI4 Stream video output interface

* External Video PHY interface

* Optional AXI4 Stream audio output interface

* Optional multi stream video support(MST)

* AXI IIC Controller support to program DP159 retimer

* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

DisplayPort TX Subsystem (1.0)

* Version 1.0

* Initial Release

* DisplayPort TX subsystem with 1/2/4 lanes

* AXI4 Stream video input interface

* External Video PHY interface

* Optional AXI4 Stream audio input interface

* Optional multi stream video support(MST)

* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

Distributed Memory Generator (8.0)

* Version 8.0 (Rev. 9)

* No changes

Divider Generator (5.1)

* Version 5.1 (Rev. 9)

* Revision change in one or more subcores

ECC (2.0)

* Version 2.0 (Rev. 10)

* Revision change in one or more subcores

Ethernet PHY MII to Reduced MII (2.0)

* Version 2.0 (Rev. 8)

* No changes

FIFO Generator (13.0)

* Version 13.0 (Rev. 1)

* Fixed safety circuit related warnings in Behavioral model

* Revision change in one or more subcores

FIR Compiler (7.2)

* Version 7.2 (Rev. 5)

* Correction to GUI reported Calculated Coefficients for Transpose Interpolation filters.

* Revision change in one or more subcores

Fast Fourier Transform (9.0)

* Version 9.0 (Rev. 9)

* Revision change in one or more subcores

Fixed Interval Timer (2.0)

* Version 2.0 (Rev. 6)

* No changes

Floating-point (7.1)

* Version 7.1 (Rev. 1)

* Revision change in one or more subcores

G.709 FEC Encoder/Decoder (2.2)

* Version 2.2 (Rev. 2)

* Added underflow protection to internal DSTS packet counter to avoid wrap-around under repeated Start-of-Frame misalignment conditions.

* Revision change in one or more subcores

G.975.1 EFEC I.4 Encoder/Decoder (1.0)

* Version 1.0 (Rev. 11)

* Revision change in one or more subcores

G.975.1 EFEC I.7 Encoder/Decoder (2.0)

* Version 2.0 (Rev. 11)

* Revision change in one or more subcores

Gamma Correction (7.0)

* Version 7.0 (Rev. 8)

* No changes

Gmii to Rgmii (4.0)

* Version 4.0 (Rev. 2)

* Support for Zynquplus devices

HDMI 1.4/2.0 Receiver (1.0)

* Version 1.0

* Initial release

HDMI 1.4/2.0 Receiver Subsystem (1.0)

* Version 1.0

* Initial Release

* HDMI 1.4 and 2.0 Sink

* Single, dual, and quad pixel-wide video interface

* Video resolutions up to UHD @ 60 fps

* Video encoding RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2, and YCbCr 4:2:0

* Deep color support (24, 30, 36 and 48-bits per pixel)

* Audio support for up to 8 channels and sample rates up to 192 kHz

* Supports info frames, DDC, EDID, hot plug, SCDC and scrambler

* Optional HDCP 1.4 support

* Supports Video and Audio over AXI-S and control/status over AXI-lite interfaces

HDMI 1.4/2.0 Transmitter (1.0)

* Version 1.0

* Initial release

HDMI 1.4/2.0 Transmitter Subsystem (1.0)

* Version 1.0

* Initial Release

* HDMI 1.4 and 2.0 Source

* Single, dual, and quad pixel-wide video interface

* Video resolutions up to UHD @ 60 fps

* Video encoding RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2, and YCbCr 4:2:0

* Deep color support (24, 30, 36 and 48-bits per pixel)

* Audio support for up to 8 channels and sample rates up to 192 kHz

* Supports info frames, DDC, EDID, hot plug, SCDC and scrambler

* Optional HDCP 1.4 support

* Supports Video and Audio over AXI-S and control/status over AXI-lite interfaces

High Speed SelectIO Wizard (2.0)

* Version 2.0

* No changes

IBERT 7 Series GTH (3.0)

* Version 3.0 (Rev. 11)

* Revision change in one or more subcores

IBERT 7 Series GTP (3.0)

* Version 3.0 (Rev. 10)

* Added device support for Defense Grade 7 Series Artix Extensions to include lower power additions.

* Revision change in one or more subcores

IBERT 7 Series GTX (3.0)

* Version 3.0 (Rev. 11)

* Added device support for Zynq Extensions to include lower power additions Zynq 7Z100.

* Revision change in one or more subcores

IBERT 7 Series GTZ (3.1)

* Version 3.1 (Rev. 8)

* No changes

IBERT UltraScale GTH (1.3)

* Version 1.3 (Rev. 1)

* Updated DRP address and xsdb regs for UltraScale plus.

* Revision change in one or more subcores

IBERT UltraScale GTY (1.2)

* Version 1.2 (Rev. 1)

* No change.

* Revision change in one or more subcores

IEEE 802.3bj RS-FEC (1.0)

* Version 1.0 (Rev. 3)

* Non functional change to stop trailing non-0 output on Tx_serdes_data

* Adds support for UltraScale+ devices

* Revision change in one or more subcores

ILA (Integrated Logic Analyzer) (6.0)

* Version 6.0 (Rev. 1)

* No change

* Revision change in one or more subcores

IOModule (3.0)

* Version 3.0 (Rev. 3)

* No changes

Image Enhancement (8.0)

* Version 8.0 (Rev. 8)

* No changes

Interlaken (1.8)

* Version 1.8

* OOBFC constraints updated and included OOBFC generator and monitor

* Added kintex095 ffva1156 package support

* Added Zynq UltraScale plus devices support

* Revision change in one or more subcores

Interleaver/De-interleaver (8.0)

* Version 8.0 (Rev. 8)

* Revision change in one or more subcores

JESD204 (6.2)

* Version 6.2 (Rev. 1)

* Version register is now automatically set by Vivado during core generation

* Fixed issue where changing the number of active lanes caused Rx configurations to never assert valid data (AR65782)

* Revision change in one or more subcores

JESD204 PHY (3.0)

* Version 3.0 (Rev. 1)

* Version register is now automatically set by Vivado during core generation

* Improved logic around reset_done output in 7-Series configurations. A tx/rx_reset_gt will cause this output to go low.

* Revision change in one or more subcores

JTAG to AXI Master (1.1)

* Version 1.1 (Rev. 1)

* Revision change in one or more subcores

LMB BRAM Controller (4.0)

* Version 4.0 (Rev. 7)

* No changes

LTE DL Channel Encoder (3.0)

* Version 3.0 (Rev. 9)

* Revision change in one or more subcores

LTE Fast Fourier Transform (2.0)

* Version 2.0 (Rev. 10)

* Revision change in one or more subcores

LTE PUCCH Receiver (2.0)

* Version 2.0 (Rev. 9)

* Revision change in one or more subcores

LTE RACH Detector (2.0)

* Version 2.0 (Rev. 9)

* Revision change in one or more subcores

LTE UL Channel Decoder (4.0)

* Version 4.0 (Rev. 9)

* Disable internal coverpoint checks, no functional changes

* Revision change in one or more subcores

Local Memory Bus (LMB) 1.0 (3.0)

* Version 3.0 (Rev. 7)

* No changes

MIPI CSI-2 Rx Controller (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

MIPI CSI-2 Rx Subsystem (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

MIPI D-PHY (1.0)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores

Mailbox (2.1)

* Version 2.1 (Rev. 5)

* No changes

Memory Helper Core (1.1)

* Version 1.1

* Support for Vivado 2015.4

Memory Interface Generator (MIG 7 Series) (2.4)

* Version 2.4 (Rev. 1)

* Vivado 2015.4 software support.

MicroBlaze (9.5)

* Version 9.5 (Rev. 3)

* Improved automatic assignment of cache addresses to select largest address segment

MicroBlaze Debug Module (MDM) (3.2)

* Version 3.2 (Rev. 4)

* No changes

MicroBlaze MCS (2.3)

* Version 2.3 (Rev. 3)

* Updated documentation links

* Revision change in one or more subcores

Multiplier (12.0)

* Version 12.0 (Rev. 10)

* Revision change in one or more subcores

Multiply Adder (3.0)

* Version 3.0 (Rev. 8)

* Minor fix to GUI to ensure field update occurs correctly.

* Revision change in one or more subcores

Mutex (2.1)

* Version 2.1 (Rev. 5)

* No changes

Partial Reconfiguration Controller (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores

Partial Reconfiguration Decoupler (1.0)

* Version 1.0 (Rev. 1)

* Removed support for FREQ_HZ on clocks that appear within interfaces. This was incompatible with other IP and IPI

* Made the CONFIG.VLNV property case sensitive to match other parts of the tool flow.

* Fixed a bug in IPI where manually managed disabled signals were re-enabled after validation.

* Fixed a bug where optional AXI4LITE signals were not enabled after IPI validation.

* Fixed a bug in IPI validation. The READ_WRITE_MODE was not being used to control signal presence.

* Fixed a bug in IPI validation. Interface parameters were not being pushed onto the slave interfaces, so they were not being propagated

* Fixed a bug in IPI where write_bd_tcl would create a file that didn't contain the decoupler's configuration information.

* Fixed a bug in IPI validation. Not all signals were being propagated as expected.

Peak Cancellation Crest Factor Reduction (6.0)

* Version 6.0 (Rev. 3)

* Warning fix for Kintex UltraScale plus devices

* Revision change in one or more subcores

Processor System Reset (5.0)

* Version 5.0 (Rev. 8)

* No changes

QDRII+ SRAM (MIG) (1.1)

* Version 1.1

* Support for Vivado 2015.4

* Revision change in one or more subcores

* Fixed lint warnings

* Fixed a couple simulation issues

* Revision change in one or more subcores

QSGMII (3.3)

* Version 3.3 (Rev. 3)

* Addition of False path constraint to RST pin of IDELAYCTRL for UltraScale devices

* Revision change in one or more subcores

RAM-based Shift Register (12.0)

* Version 12.0 (Rev. 8)

* Revision change in one or more subcores

RGB to YCrCb Color-Space Converter (7.1)

* Version 7.1 (Rev. 6)

* No changes

RLDRAM3 (MIG) (1.1)

* Version 1.1

* Updated for 2015.4

* Updated XSDB BURST_DATA_BUS registers

* Improved timing

* Added Advanced Traffic Generator support for RLDRAM3

* Revision change in one or more subcores

RXAUI (4.3)

* Version 4.3 (Rev. 3)

* Updated scripts for upgrade from previous release

* Revision change in one or more subcores

Reed-Solomon Decoder (9.0)

* Version 9.0 (Rev. 10)

* Fixed bug which could cause the System Generator block GUI to hang when the IP was parameterized

* Revision change in one or more subcores

Reed-Solomon Encoder (9.0)

* Version 9.0 (Rev. 9)

* Revision change in one or more subcores

S/PDIF (2.0)

* Version 2.0 (Rev. 10)

* Revision change in one or more subcores

SMPTE 2022-1/2 Video over IP Receiver (2.0)

* Version 2.0 (Rev. 4)

* Revision change in one or more subcores

SMPTE 2022-1/2 Video over IP Transmitter (2.0)

* Version 2.0 (Rev. 4)

* Revision change in one or more subcores

SMPTE SD/HD/3G-SDI (3.0)

* Version 3.0 (Rev. 6)

* No changes

SMPTE UHD-SDI (1.0)

* Version 1.0 (Rev. 1)

* No changes

SMPTE2022-5/6 Video over IP Receiver (5.0)

* Version 5.0 (Rev. 3)

* Revision change in one or more subcores

SMPTE2022-5/6 Video over IP Transmitter (4.0)

* Version 4.0 (Rev. 5)

* Revision change in one or more subcores

SPI-4.2 (13.0)

* Version 13.0 (Rev. 7)

* No changes

SelectIO Interface Wizard (5.1)

* Version 5.1 (Rev. 6)

* No changes

Serial RapidIO Gen2 (4.0)

* Version 4.0 (Rev. 2)

* corrected gt_rxlpmen_in value.

* Revision change in one or more subcores

Soft Error Mitigation (4.1)

* Version 4.1 (Rev. 5)

* No changes

System Cache (3.1)

* Version 3.1 (Rev. 2)

* No changes

System Management Wizard (1.2)

* Version 1.2 (Rev. 3)

* No functional changes, Internal GUI changes.

Timer Sync 1588 (1.2)

* Version 1.2 (Rev. 3)

* No changes

Tri Mode Ethernet MAC (9.0)

* Version 9.0 (Rev. 3)

* Updated TX path latency values for 1588 mode for UltraScale family devices

* Fixed bug in legacy pause frame transmission for 10/100 Mbps line rates, wherein the transmitted pause frame had zero value in time field

* Fixed bug in legacy pause frame receive logic, wherein the received pause frame was presented as a valid frame on the RX AXI Stream Interface, for some cases, when the core is generated with 1588 inline timestamp feature

* UltraScale Plus device support is limited to simulation only. Timing violations may bee seen when implementing the IP on UltraScale Plus devices

* Revision change in one or more subcores

UltraScale FPGAs Transceivers Wizard (1.6)

* Version 1.6 (Rev. 1)

* Improved performance and functionality of UltraScale+ GTH and GTY serial transceivers via parameter updates

* Added support for newer UltraScale+ GTY serial transceiver simulation and device models

* Added new transceiver configuration preset option

* Added support for UltraScale -1H and -1HV speed grades

* Revision change in one or more subcores

UltraScale Soft Error Mitigation (3.0)

* Version 3.0 (Rev. 1)

* Resolve AR65552, XCVU190 classification makedata.tcl is incorrect

* Update default configuration for IP to work out-of-the-box when kcu105 and vcu108 evaluation boards are targeted

UltraScale+ PCI Express Integrated Block (1.0)

* Version 1.0 (Rev. 1)

* Integrated new GTY and GTH wrapper changes

* Added support for few more Devices/Packages

* Revision change in one or more subcores

UltraScale FPGA Gen3 Integrated Block for PCI Express (4.1)

* Version 4.1 (Rev. 1)

* Added support for ffva1156 package for xcku095 device

* Revision change in one or more subcores

VIO (Virtual Input/Output) (3.0)

* Version 3.0 (Rev. 10)

* Revision change in one or more subcores

Video Deinterlacer (4.0)

* Version 4.0 (Rev. 9)

* No changes

Video In to AXI4-Stream (4.0)

* Version 4.0 (Rev. 1)

* Fixed clock domain crossing problem related to the axis_enable input port

* Revision change in one or more subcores

Video On Screen Display (6.0)

* Version 6.0 (Rev. 9)

* No changes

Video PHY Controller (2.0)

* Version 2.0

* Initial Release

* HDMI protocol support added for GTXE2 and GTHE3

* DisplayPort protocol support for GTHE3

* Revision change in one of the subcore

* Revision change in one or more subcores

Video Processing Subsystem (1.0)

* Version 1.0 (Rev. 1)

* Increased maximum resolution to 4096x2160

* Revision change in one or more subcores

Video Scaler (8.1)

* Version 8.1 (Rev. 7)

* Changed supported_families to discontinued .Please select the Video Processing Subsystem

Video Test Pattern Generator (7.0)

* Version 7.0 (Rev. 1)

* Increased maximum resolution to 4096x2160

* Revision change in one or more subcores

Video Timing Controller (6.1)

* Version 6.1 (Rev. 6)

* No changes

Video over IP FEC Receiver (1.0)

* Version 1.0 (Rev. 2)

* Added arbiter for AXI-MM0 wr, AXI-MM1 wr and AXI-MM0 read

* Added out-of-range counter

* Fixed reorder counter

* Limiting buffer depth to 256

* Swap back the L and D in event send out

* Bug fix on wrong OOR packets due to BRAM port A read access while BRAM port B writes.

* Revision change in one or more subcores

Video over IP FEC Transmitter (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.1)

* Version 4.1 (Rev. 1)

* Fixed unresolved instances of sys_clk_gen used in pipe mode simulations. This module is now delivered in 'source' directory

Viterbi Decoder (9.1)

* Version 9.1 (Rev. 5)

* Revision change in one or more subcores

XADC Wizard (3.2)

* Version 3.2

* No changes

XAUI (12.2)

* Version 12.2 (Rev. 3)

* Updated scripts for upgrade from previous release

* Revision change in one or more subcores

YCrCb to RGB Color-Space Converter (7.1)

* Version 7.1 (Rev. 6)

* No changes

ZYNQ UltraScale+ MPSoC (1.0)

* Version 1.0 (Rev. 2)

* Added appropriate GT lanes for DP

* Voltage swing level settings for GT lanes

* Reference clocks of PLL selectable

ZYNQ7 Processing System (5.5)

* Version 5.5 (Rev. 3)

* No changes

ZYNQ7 Processing System BFM (2.0)

* Version 2.0 (Rev. 5)

* No changes

axi_sg (4.1)

* Version 4.1 (Rev. 2)

* No changes

interrupt_controller (3.1)

* Version 3.1 (Rev. 3)

* Support owner information updated

lib_bmg (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores

lib_cdc (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_fifo (1.0)

* Version 1.0 (Rev. 4)

* Revision change in one or more subcores

lib_pkg (1.0)

* Version 1.0 (Rev. 2)

* No changes

lib_srl_fifo (1.0)

* Version 1.0 (Rev. 2)

* No changes