AR# 55460: JESD204 V4.0 - AXI4-Lite address decode incorrect for 8bit and 16bit writes to the Rx Buffer Delay and Frames per Multiframe register
AR# 55460
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JESD204 V4.0 - AXI4-Lite address decode incorrect for 8bit and 16bit writes to the Rx Buffer Delay and Frames per Multiframe register
描述
This Issue affects the JESD204 V4.0 IP Core released in Vivado 2013.1
The address decode for 8-bit and 16-bitsub-word writes does not work correctly for address 0x03 (Rx Buffer Delay and Frames per Multiframe).
Full 32 bit word writes work as expected.
解决方案
The RTL file provided with the core (<component_name>_block.v) requires the following change:
1) Look for the decode of Bus2IP_WrCE[60] by searching for the comment "// 0x03 Frames per multiframe and Receive buffer delay"
2) Change the line: if (Bus2IP_BE[2]) to: if (Bus2IP_BE[1])
and the line: if (Bus2IP_BE[3]) to: if (Bus2IP_BE[2])
Note:
1) This change must be done in a file editor outside of the Vivado GUI as the file is write protected within Vivado. 2) This change will be overwritten if you regenerate the IP (when updating core parameters or when running a simulation for example).