AR# 63724: 2014.4.1 Vivado IP Release Notes - All IP Change Log Information
AR# 63724
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2014.4.1 Vivado IP Release Notes - All IP Change Log Information
描述
This answer record contains a comprehensive list of IP change log information from Vivado 2014.4.1 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.
解决方案
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100G Ethernet (1.4) * Version 1.4 (Rev. 1) * Support for latest ultra-scale devices
32-bit Initiator/Target for PCI (7-Series) (5.0) * Version 5.0 (Rev. 6) * No changes
3GPP LTE Channel Estimator (2.0) * Version 2.0 (Rev. 7) * No changes
3GPP LTE MIMO Decoder (3.0) * Version 3.0 (Rev. 7) * No changes
3GPP LTE MIMO Encoder (4.0) * Version 4.0 (Rev. 6) * No changes
3GPP Mixed Mode Turbo Decoder (2.0) * Version 2.0 (Rev. 7) * No changes
3GPP Turbo Encoder (5.0) * Version 5.0 (Rev. 6) * No changes
3GPPLTE Turbo Encoder (4.0) * Version 4.0 (Rev. 6) * No changes
64-bit Initiator/Target for PCI (7-Series) (5.0) * Version 5.0 (Rev. 6) * No changes
7 Series FPGAs Transceivers Wizard (3.4) * Version 3.4 (Rev. 1) * No changes
7 Series Integrated Block for PCI Express (3.0) * Version 3.0 (Rev. 4) * No changes
AHB-Lite to AXI Bridge (3.0) * Version 3.0 (Rev. 2) * No changes
AXI 10G-Ethernet Subsystem (2.0) * Version 2.0 (Rev. 2) * Update to UltraScale GT Wizard v1.5 * 1588 permutations using the Time-of-Day format: an issue has been fixed in the receiver timestamp whereby the seconds field could occasionally be in advance by 1 second * Make it easier for the Auto-Negotiation Block to lock to and parse incoming data
AXI AHBLite Bridge (3.0) * Version 3.0 (Rev. 2) * No changes
AXI APB Bridge (3.0) * Version 3.0 (Rev. 2) * No changes
AXI BFM Cores (5.0) * Version 5.0 (Rev. 4) * No changes
AXI BRAM Controller (4.0) * Version 4.0 (Rev. 3) * No changes
AXI Bridge for PCI Express Gen3 Subsystem (1.0) * Version 1.0 (Rev. 2) * Added support for new packages flvb1760,ffvd1517,ffvc1517,flva2104,flvd1517 and flvb2104. * Fixed issue with MRd transactions during link down (AR * Added support for GUI option to select PLL_TYPE for Gen2 Speed. CPLL (Optional) and QPLL1 (Default) * Added support for GUI option to select CORE_CLK_FREQ for Gen3 x1/x2/x4. 250 MHz (Default) and 500 MHz (Optional) * Removed x8G3 support for -1/-1L speedgrades * Added PCIe specific production settings for VU095-ES2 * Removed support of x4G3 of 128 bit axis interface and 250 MHz user clock for -1/-1L speedgrade * Added PIPELINE in RTL for CFGMAXPAYLOAD and CFGMAXREADREQUEST signals to improve timing
AXI CAN (5.0) * Version 5.0 (Rev. 7) * No changes
AXI Central Direct Memory Access (4.1) * Version 4.1 (Rev. 4) * No changes
AXI Chip2Chip Bridge (4.2) * Version 4.2 (Rev. 3) * No changes
AXI Clock Converter (2.1) * Version 2.1 (Rev. 3) * No changes
AXI Crossbar (2.1) * Version 2.1 (Rev. 5) * No changes
AXI Data FIFO (2.1) * Version 2.1 (Rev. 3) * No changes
AXI Data Width Converter (2.1) * Version 2.1 (Rev. 4) * No changes
AXI DataMover (5.1) * Version 5.1 (Rev. 5) * No changes
AXI Direct Memory Access (7.1) * Version 7.1 (Rev. 4) * No changes
AXI EMC (3.0) * Version 3.0 (Rev. 3) * No changes
AXI EPC (2.0) * Version 2.0 (Rev. 6) * No changes
AXI Ethernet Buffer (2.0) * Version 2.0 (Rev. 6) * No changes
AXI Ethernet Clocking (2.0) * Version 2.0 (Rev. 1) * No changes
AXI Ethernet Subsystem (6.2) * Version 6.2 (Rev. 1) * No changes
AXI EthernetLite (3.0) * Version 3.0 (Rev. 2) * No changes
AXI GPIO (2.0) * Version 2.0 (Rev. 6) * No changes
AXI HWICAP (3.0) * Version 3.0 (Rev. 7) * No changes
AXI IIC (2.0) * Version 2.0 (Rev. 7) * No changes
AXI Interconnect (2.1) * Version 2.1 (Rev. 5) * No changes
AXI Interrupt Controller (4.1) * Version 4.1 (Rev. 2) * No changes
AXI Lite IPIF (3.0) * Version 3.0 (Rev. 1) * No changes
AXI MMU (2.1) * Version 2.1 (Rev. 2) * No changes
AXI Master Burst (2.0) * Version 2.0 (Rev. 5) * No changes
AXI Memory Mapped To PCI Express (2.5) * Version 2.5 (Rev. 1) * No changes
AXI Memory Mapped to Stream Mapper (1.1) * Version 1.1 (Rev. 3) * No changes
AXI Performance Monitor (5.0) * Version 5.0 (Rev. 5) * No changes
AXI Protocol Checker (1.1) * Version 1.1 (Rev. 5) * No changes
AXI Protocol Converter (2.1) * Version 2.1 (Rev. 4) * No changes
AXI Quad SPI (3.2) * Version 3.2 (Rev. 2) * No changes
AXI Register Slice (2.1) * Version 2.1 (Rev. 4) * No changes
AXI TFT Controller (2.0) * Version 2.0 (Rev. 7) * No changes
AXI Timebase Watchdog Timer (2.0) * Version 2.0 (Rev. 6) * No changes
AXI Timer (2.0) * Version 2.0 (Rev. 6) * No changes
AXI Traffic Generator (2.0) * Version 2.0 (Rev. 5) * No changes
AXI UART16550 (2.0) * Version 2.0 (Rev. 6) * No changes
AXI USB2 Device (5.0) * Version 5.0 (Rev. 5) * No changes
AXI Uartlite (2.0) * Version 2.0 (Rev. 7) * No changes
AXI Video Direct Memory Access (6.2) * Version 6.2 (Rev. 2) * No changes
AXI Virtual FIFO Controller (2.0) * Version 2.0 (Rev. 6) * No changes
AXI-Stream FIFO (4.1) * Version 4.1 (Rev. 1) * No changes
AXI4-Stream Accelerator Adapter (2.1) * Version 2.1 (Rev. 2)
* No changes
AXI4-Stream Broadcaster (1.1) * Version 1.1 (Rev. 4) * No changes
AXI4-Stream Clock Converter (1.1) * Version 1.1 (Rev. 5) * No changes
AXI4-Stream Combiner (1.1) * Version 1.1 (Rev. 3) * No changes
AXI4-Stream Data FIFO (1.1) * Version 1.1 (Rev. 5) * No changes
AXI4-Stream Data Width Converter (1.1) * Version 1.1 (Rev. 3) * No changes
AXI4-Stream Interconnect (2.1) * Version 1.1 * No changes
AXI4-Stream Protocol Checker (1.1) * Version 1.1 (Rev. 4) * No changes
AXI4-Stream Register Slice (1.1) * Version 1.1 (Rev. 4) * No changes
AXI4-Stream Subset Converter (1.1) * Version 1.1 (Rev. 4) * No changes
AXI4-Stream Switch (1.1) * Version 1.1 (Rev. 4) * No changes
AXI4-Stream to Video Out (3.0) * Version 3.0 (Rev. 6) * No changes
Accumulator (12.0) * Version 12.0 (Rev. 5) * No changes
Adder/Subtracter (12.0) * Version 12.0 (Rev. 5) * No changes
Aurora 64B66B (9.3) * Version 9.3 (Rev. 2) * UltraScale GT Wizard version updated
Aurora 8B10B (10.3) * Version 10.3 (Rev. 2) * UltraScale GT Wizard version updated
Binary Counter (12.0) * Version 12.0 (Rev. 5) * No changes
Block Memory Generator (8.2) * Version 8.2 (Rev. 4) * Support UltraScale device package changes, no functional changes
CIC Compiler (4.0) * Version 4.0 (Rev. 6) * No changes
CORDIC (6.0) * Version 6.0 (Rev. 6) * No changes
CPRI (8.3) * Version 8.3 (Rev. 2) * Updated to use version 1.5 of the UltraScale GT Wizard.
Chroma Resampler (4.0) * Version 4.0 (Rev. 5) * No changes
Clocking Wizard (5.1) * Version 5.1 (Rev. 5)
* No changes
Color Correction Matrix (6.0) * Version 6.0 (Rev. 6) * No changes
Color Filter Array Interpolation (7.0) * Version 7.0 (Rev. 5) * No changes
Complex Multiplier (6.0) * Version 6.0 (Rev. 6) * No changes
Convolution Encoder (9.0) * Version 9.0 (Rev. 6) * No changes
DDS Compiler (6.0) * Version 6.0 (Rev. 7) * No changes
DSP48 Macro (3.0) * Version 3.0 (Rev. 7) * No changes
DUC/DDC Compiler (3.0) * Version 3.0 (Rev. 6) * No changes
Discrete Fourier Transform (4.0) * Version 4.0 (Rev. 6) * No changes
DisplayPort (5.0) * Version 5.0 (Rev. 1) * No changes
Distributed Memory Generator (8.0) * Version 8.0 (Rev. 7) * No changes
Divider Generator (5.1) * Version 5.1 (Rev. 5)
* No changes
ECC (2.0) * Version 2.0 (Rev. 7) * No changes
Ethernet 1000BASE-X PCS/PMA or SGMII (14.3) * Version 14.3 (Rev. 2) * 1588 permutations using the Time-of-Day format, An issue has been fixed in the receiver timestamp whereby the seconds field could occasionally be in advance by 1 second. * Uprev of UltraScale wizard to version 1.5.
Ethernet PHY MII to Reduced MII (2.0) * Version 2.0 (Rev. 6) * No changes
FIFO Generator (12.0) * Version 12.0 (Rev. 3) * No changes
FIR Compiler (7.2) * Version 7.2 (Rev. 1) * No changes
Fast Fourier Transform (9.0) * Version 9.0 (Rev. 6) * No changes
Fixed Interval Timer (2.0) * Version 2.0 (Rev. 4) * No changes
Floating-point (7.0) * Version 7.0 (Rev. 7) * No changes
G.709 FEC Encoder/Decoder (2.1) * Version 2.1 (Rev. 4) * No changes
G.975.1 EFEC I.4 Encoder/Decoder (1.0) * Version 1.0 (Rev. 7) * No changes
G.975.1 EFEC I.7 Encoder/Decoder (2.0) * Version 2.0 (Rev. 7) * No changes
Gamma Correction (7.0) * Version 7.0 (Rev. 6) * No changes
Gmii to Rgmii (3.0) * Version 3.0 (Rev. 4) * No changes
High Speed SelectIO Wizard (1.1) * Version 1.1 (Rev. 1)
* No changes
IBERT 7 Series GTH (3.0) * Version 3.0 (Rev. 7) * No changes
IBERT 7 Series GTP (3.0) * Version 3.0 (Rev. 7) * No changes
IBERT 7 Series GTX (3.0) * Version 3.0 (Rev. 7) * No changes
IBERT 7 Series GTZ (3.1) * Version 3.1 (Rev. 5) * No changes
IBERT UltraScale GTH (1.1) * Version 1.1 (Rev. 2)
* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
* Updated files to use gtwizard_ultrascale_v1_5
* Disabled cpll_cal_block for production silicon.
IBERT UltraScale GTY (1.0) * Version 1.0 (Rev. 2) * Added new parameter C_USE_MDM. * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time * Updated files to use gtwizard_ultrascale_v1_5
ILA (Integrated Logic Analyzer) (5.0) * Version 5.0 (Rev. 2) * Updated example XDC pin location constraints for new devices
IOModule (3.0) * Version 3.0 * No changes
Image Enhancement (8.0) * Version 8.0 (Rev. 6) * No changes
Interlaken (1.4) * Version 1.4 (Rev. 1) * Updated latest UltraScale devices/packages support * Multiple IBFUDS instantiated and added differential clocl pin pairs when Lane_rate > 16.375 Gb/s as per UG578
Interleaver/De-interleaver (8.0) * Version 8.0 (Rev. 5) * No changes
JESD204 (6.0) * Version 6.0 (Rev. 2) * Updated UltraScale Transceiver Wizard to version 1.5
JESD204 PHY (1.0) * Version 1.0 (Rev. 2) * Updated UltraScale Transceiver Wizard to version 1.5
JTAG to AXI Master (1.0) * Version 1.0 (Rev. 6)
* Updated example XDC pin location constraints for new devices
LMB BRAM Controller (4.0) * Version 4.0 (Rev. 5) * No changes
LTE DL Channel Encoder (3.0) * Version 3.0 (Rev. 6) * No changes
LTE Fast Fourier Transform (2.0) * Version 2.0 (Rev. 6) * No changes
LTE PUCCH Receiver (2.0) * Version 2.0 (Rev. 6) * No changes
LTE RACH Detector (2.0) * Version 2.0 (Rev. 6) * No changes
LTE UL Channel Decoder (4.0) * Version 4.0 (Rev. 6) * No changes
Local Memory Bus (LMB) 1.0 (3.0) * Version 3.0 (Rev. 5) * No changes
Mailbox (2.1) * Version 2.1 (Rev. 2) * No changes
Memory Interface Generator (MIG 7 Series) (2.3) * Version 2.3 * No changes
Memory Interface Generator (MIG) (6.1) * Version 6.1 (Rev. 1) * No changes in logic from version 6.1
MicroBlaze (9.4) * Version 9.4 (Rev. 1) * No changes
MicroBlaze Debug Module (MDM) (3.2) * Version 3.2 (Rev. 1) * No changes
MicroBlaze MCS (2.2) * Version 2.2 (Rev. 3) * No changes
Multiplier (12.0) * Version 12.0 (Rev. 6) * No changes
Multiply Adder (3.0) * Version 3.0 (Rev. 5) * No changes
Mutex (2.1) * Version 2.1 (Rev. 2) * No changes
Peak Cancellation Crest Factor Reduction (5.0) * Version 5.0 (Rev. 4) * No changes
Processor System Reset (5.0) * Version 5.0 (Rev. 6) * No changes
QSGMII (3.2) * Version 3.2 (Rev. 4) * Uprev of UltraScale wizard to version 1.5.
RAM-based Shift Register (12.0) * Version 12.0 (Rev. 5) * No changes
RGB to YCrCb Color-Space Converter (7.1) * Version 7.1 (Rev. 4) * No changes
RXAUI (4.2) * Version 4.2 (Rev. 3) * No changes
Reed-Solomon Decoder (9.0) * Version 9.0 (Rev. 7) * No changes
Reed-Solomon Encoder (9.0) * Version 9.0 (Rev. 6) * No changes
S/PDIF (2.0) * Version 2.0 (Rev. 7) * No changes
SMPTE 2022-1/2 Video over IP Receiver (2.0) * Version 2.0 (Rev. 1) * No changes
SMPTE 2022-1/2 Video over IP Transmitter (2.0) * Version 2.0 (Rev. 1) * No changes
SMPTE SD/HD/3G-SDI (3.0) * Version 3.0 (Rev. 3) * No changes
SMPTE2022-5/6 Video over IP Receiver (4.0) * Version 4.0 (Rev. 1) * No changes
SMPTE2022-5/6 Video over IP Transmitter (4.0) * Version 4.0 (Rev. 1) * No changes
SPI-4.2 (13.0) * Version 13.0 (Rev. 6) * No changes
SelectIO Interface Wizard (5.1) * Version 5.1 (Rev. 4)
* No changes
Serial RapidIO Gen2 (3.2) * Version 3.2 (Rev. 2) * Updated UltraScale GT wizard production version to 1.5
Soft Error Mitigation (4.1) * Version 4.1 (Rev. 3) * No changes
System Cache (3.0) * Version 3.0 (Rev. 5) * No changes
System Management Wizard (1.1) * Version 1.1 (Rev. 1)
* No changes
Ten Gigabit Ethernet MAC (14.0) * Version 14.0 (Rev. 2) * Updated MDIO logic to ensure back to back transactions start correctly * Updated RX MMCM phase shift to improve RX XGMII timing for Kintex UltraScale * Added constraints for XGMII to prevent incorrect edge being timed against each other
Ten Gigabit Ethernet PCS/PMA (10GBASE-R/KR) (5.0) * Version 5.0 (Rev. 2) * Make it easier for AutoNegotiation Block to lock to and parse incoming data * Update to UltraScale GT Wizard v1.5 * Connected gt_powergood from UltraScale transceiver to shared clock and reset block to control the release of QPLLRESET
Test Pattern Generator (6.0) * Version 6.0 (Rev. 3) * No changes
Timer Sync 1588 (1.2) * Version 1.2 (Rev. 2) * No changes
Tri Mode Ethernet MAC (8.3) * Version 8.3 (Rev. 1) * No changes
UltraScale FPGAs Transceivers Wizard (1.5) * Version 1.5 * Added several new transceiver configuration preset options * Added a recustomizable Virtual Input/Output (VIO) core instance to the example design to assist with system monitoring and analysis * Added support for new QPLL feedback divider values of 60, 75, 84, 90, 96, 112, 120, 125, and 150, providing more reference clock frequency options for any given line rate * Added support for GTY transceiver ES2-level simulation and device models * Modified connectivity between the reset controller helper block and CPLL resources in production devices, driving CPLLPD instead of CPLLRESET in accordance with Xilinx UltraScale Architecture Transceivers user guides * Improved performance of GTH and GTY transceivers via parameter updates * Improved clarity of the Wizard customization GUI channel table by displaying the SLR number for each transceiver quad, and by making its transceiver resources ordering consistent with the Physical Resources block diagram * Fixed minor Wizard customization GUI display bugs * Reduced maximum GTY line rate in Virtex UltraScale -3 speed grade devices from 32.75 Gb/s to 30.5 Gb/s
UltraScale FPGA Gen3 Integrated Block for PCI Express (3.1) * Version 3.1 (Rev. 2) * Enabled 1.5 GT Wizard * Added support for new packages flvb1760,ffvd1517,ffvc1517,flva2104,flvd1517 and flvb2104. * Added support for GUI option to select PLL_TYPE for Gen2 Speed. CPLL (Optional) and QPLL1 (Default) * Added support for GUI option to select CORE_CLK_FREQ for Gen3 x1/x2/x4. 250 MHz (Default) and 500 MHz (Optional) * Removed x8G3 support for -1/-1L speedgrades * Added PCIe specific production settings for VU095-ES2 * Edited Insertion loss default value to 15 db from 20 db * Made GTWIZARD as default for all configurations * Removed CPLL Calibration module for Production devices and for VU095-ES2. Same applies to the static wrappers. * Added BUFG_GT_SYNC macro for sys_rst buffer * Passing PL_SIM_FAST_LINK_TRAINING parameter to speed up simulation * Added bram_req_8k.v (REQUEST) and it has BRAM WE/RE related change
VIO (Virtual Input/Output) (3.0) * Version 3.0 (Rev. 6)
* Updated example XDC pin location constraints for new devices
Video Deinterlacer (4.0) * Version 4.0 (Rev. 7) * No changes
Video In to AXI4-Stream (3.0) * Version 3.0 (Rev. 6) * No changes
Video On Screen Display (6.0) * Version 6.0 (Rev. 7) * No changes
Video Scaler (8.1) * Version 8.1 (Rev. 4) * No changes
Video Timing Controller (6.1) * Version 6.1 (Rev. 4) * No changes
Virtex-7 FPGA Gen3 Integrated Block for PCI Express (3.0) * Version 3.0 (Rev. 4) * No changes
Viterbi Decoder (9.1) * Version 9.1 (Rev. 1) * No changes
XADC Wizard (3.0) * Version 3.0 (Rev. 6)
* No changes
XAUI (12.1) * Version 12.1 (Rev. 4) * No changes
YCrCb to RGB Color-Space Converter (7.1) * Version 7.1 (Rev. 4) * No changes
ZYNQ7 Processing System (5.5) * Version 5.5
* No changes
ZYNQ7 Processing System BFM (2.0) * Version 2.0 (Rev. 3) * No changes
axi_sg (4.1) * Version 4.1 * No changes
interrupt_controller (3.1) * Version 3.1 * No changes