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  3. AR# 56078: JESD204B v4.0 - Updated RX Buffer settings for 7 Series FPGA GTX, GTP and GTH

AR# 56078

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JESD204B v4.0 - Updated RX Buffer settings for 7 Series FPGA GTX, GTP and GTH

描述

The RX Buffer can sometimes indicate an underflow on RXBUFSTATUS as the buffer full level drops below the underflow threshold. The buffer does not always completely empty and cause data errors, but the buffer settings should be updated to improve reliability and prevent the possibility of underflow.

解决方案

Update the following GTX, GTP and GTH settings to ensure there is enough space in the buffer to prevent underflow:

CLK_COR_MIN_LAT = 8
CLK_COR_MAX_LAT = 12
RXBUF_THRESH_UNDFLW = 3
RXBUF_THRESH_OVRFLW =57
RXBUF_THRESH_OVRD = TRUE

Note that the total receive latency is increased by 5 byte clock periods after this change is made.

Revision History:
06/20/2013 - Initial Release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54480 LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
AR# 56078
日期 07/01/2013
状态 Active
Type 综合文章
IP
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