This Answer Record contains the Zynq-7000 SoC Frequently Asked Questions.
NOTE: This answer record is part of the Xilinx Zynq-7000 SoC Solution Center (Xilinx Answer 52512).
The Xilinx Zynq-7000 SoC Solution Center is available to address all questions related to Zynq-7000 SoC.
Whether you are starting a new design with Zynq-7000 SoC or troubleshooting a problem, use the Zynq-7000 SoC Solution Center to guide you to the right information.
Top Frequently Asked Questions
| (Xilinx Answer 46778) | 14.1 EDK, Zynq-7000 - How do I Configure the PS DDRC? |
| (Xilinx Answer 46881) | Zynq-7000 Debug - How do I set up a third-party debug environment on the ZC702 board? |
| (Xilinx Answer 46871) | 14.2 EDK, Zynq-7000 - Which IBIS models should be used for Zynq? |
| (Xilinx Answer 46988) | Zynq-7000 Debug - How do you run ps7_init.tcl from Lauterbach? |
| (Xilinx Answer 47792) | Zynq-7000 EPP, Gigabit Ethernet - What are the supported PHY modes? |
| (Xilinx Answer 51063) | 14.1 Zynq-7000 - Why is QSPI programming not working when the feedback clock is used? |
| (Xilinx Answer 51248) | Zynq-7000 - What QSPI Clock mode/speed is supported on the ZC702? |
| (Xilinx Answer 51778) | Zynq-7000 - How should the PS DDR3 CKE signal be terminated? |
| (Xilinx Answer 46911) | EDK 14.1 Zynq-7000 - How do I create a stub for the second CPU core? |
| (Xilinx Answer 47167) | 14.1 EDK, Zynq - Why can only half of the PS DDR memory be used with MicroBlaze connected? |
| (Xilinx Answer 51790) | Zynq-7000 - How is the DDRC address mapping used? |
| (Xilinx Answer 50935) | Zynq-7000 EPP - Does VCCAUX power the Processor System (PS)? |
| (Xilinx Answer 50898) | 14.1 EDK/SDK - Are there any ECC limitations on the Zynq device DDRx controller? |
| (Xilinx Answer 51996) | Zynq-7000, DDRC - What are the Zynq Processing System DDR data sheet parameters? |
| (Xilinx Answer 52491) | 14.3 EDK, Zynq-7000 - How do I run the Zynq PS-PL AXI interfaces at the highest frequency? |
| (Xilinx Answer 52252) | Zynq-7000 SoC ZC702 Evaluation Kit TRD - Why is my 1080p60 input not being detected when using the Avnet IMAGEON FMC daughter card with the 14.1 or 14.2 TRD design? |
| (Xilinx Answer 50499) | 14.2 EDK - Toggling PS_SRST_B does not configure PL when booting from SD or QSPI using BOOT.bin |
| (Xilinx Answer 51782) | EDK-14.3,Zynq-7000: What is the default QSPI interface clock frequency used in the FSBL and How to speed it up? |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 52512 | Xilinx Zynq-7000 SoC Solution Center | N/A | N/A |
| 52511 | Zynq-7000 SoC Design Assistant | N/A | N/A |
| AR# 52540 | |
|---|---|
| 日期 | 08/13/2018 |
| 状态 | Active |
| Type | 解决方案中心 |
| 器件 | |