When programming or operating a QSPI device with a clock frequency greater than FQSPICLK2 (see DS187), MIO[8] (qspi_sclk_fb_out) can only be floated or connected to a pull-up/pull-down resistor on the PCB, and Quad-SPI external loopback must be enabled.
Check that the MIO[8] pin is not connected to any additional resistive or capacitive loads other than what is stated in the Zynq TRM when using the QSPI with the Feedback Clock mode enabled.
To program QSPI reliably with a clock that is greater than FQSPICLK2:
To program QSPI reliably with a QSPI Clock that is less than FQSPICLK2:
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
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52540 | Zynq-7000 SoC - Frequently Asked Questions | N/A | N/A |
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
51248 | Zynq-7000 - ZC702 支持什么 QSPI 时钟模式/速度? | N/A | N/A |
51235 | Zynq-7000 - 14.1/14.2 Xilinx QSPI 编程工具(SDK 和 iMPACT)支持具有外部回送功能的设计 | N/A | N/A |
AR# 51063 | |
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日期 | 10/24/2012 |
状态 | Active |
Type | 已知问题 |
器件 | |
Tools |