What are the Zynq Processing System DDR data sheet parameters? I would like to perform Hyperlynx simulation and board-level timing budget.
The Zynq Processing System DDR controller board timing parameters are provided in (DS191) and (DS187).
The Zynq Processing System DDR board-level design should follow the restrictions from the Zynq-7000 PCB Design and Pin Planning Guide (UG933).
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 52540 | Zynq-7000 SoC - Frequently Asked Questions | N/A | N/A |
| 52539 | Zynq-7000 SoC - Board Design | N/A | N/A |
| 53051 | Zynq-7000 SoC - PS DDR Controller | N/A | N/A |
| AR# 51996 | |
|---|---|
| 日期 | 05/17/2018 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 | |