This answer record collects Zynq-7000 SoC answer records related to the Processing System (PS) DDR Controller (DDRC), including common questions and known issues.
Note: This answer record is part of Xilinx Zynq-7000 SoC Solution Center (Xilinx Answer 52512).
Xilinx Zynq-7000 SoC Solution Center is available to address all questions related to Zynq-7000 SoC.
Whether you are starting a new design with Zynq-7000 SoC or troubleshooting a problem, use the Zynq-7000 SoC Solution Center to guide you to the right information.
Top Issues on DDR Board Design
| (Xilinx Answer 51996) | Zynq-7000, DDRC - What are the Zynq Processing System DDR data sheet parameters? |
| (Xilinx Answer 46871) | 14.2 EDK, Zynq-7000 - Which IBIS models should be used for Zynq devices? |
| (Xilinx Answer 51778) | Zynq-7000 - How should the PS DDR3 CKE signal be terminated? |
| (Xilinx Answer 46723) | Zynq-7000 SoC - Can I swap PS DDR DQ pins for board design? |
| (Xilinx Answer 52539) | Zynq-7000 SoC - Board Design Article |
| (Xilinx Answer 46778) | Zynq-7000 - How do I configure the PS DDRC board parameters? |
| (Xilinx Answer 59836) | Zynq-7000 SoC - How does the DDRC training work? |
| (Xilinx Answer 54398) | Zynq-7000 SOC - When using a faster DDR device than the clock frequency, which timing specifications can be used? |
| (Xilinx Answer 51790) | Zynq-7000 - How is the DDRC address mapping used? |
| (Xilinx Answer 53039) | 14.3 EDK, Zynq-7000 DDRC - Why is the PS7 DDR Configuration limit DQS to Clock delay to -.100ns? |
Top Issues on DDR Debug
| (Xilinx Answer 60454) | Design Advisory Zynq-7000 PS DDR Controller - DDR IO's are not properly configured in ISE/EDK and Vivado 2013.3 and earlier |
| (Xilinx Answer 62042) | Zynq-7000 SoC, Vivado 2014.2 - PS DDRC asserts ODT during reads |
| (Xilinx Answer 51074) | 14.2 EDK, Zynq-7000 - PS DDRC with ECC does not function |
| (Xilinx Answer 47516) | Zynq-7000 SoC, DDR - Controller Mishandles STREX Instruction |
| (Xilinx Answer 47484) | Zynq-7000 SoC, AXI - Deadlock Can Occur when OCM and DDR are Accessed by AXI_HP Article |
| (Xilinx Answer 47514) | Zynq-7000 SoC, DDR - DDR3 Starts DRAM Clock too Early after Exiting Self-Refresh |
Related Documentation
Zynq-7000 SOC Technical Reference Manual:
Chapter 10: DDR Memory Controller
Zynq-7000 SoC PCB Design and Pin Planning Guide
Zynq-7000 SoC (XC7Z010 and XC7Z020) Data Sheet: DC and AC Switching Characteristics
Zynq-7000 SoC (XC7Z030 and XC7Z045) Data Sheet: DC and AC Switching Characteristics
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 52511 | Zynq-7000 SoC Design Assistant | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 51996 | Zynq-7000, DDRC - What are the Zynq Processing System DDR data sheet parameters? | N/A | N/A |
| 46871 | Zynq-7000 - Which IBIS models should be used for Zynq-7000 devices? | N/A | N/A |
| 52539 | Zynq-7000 SoC - Board Design | N/A | N/A |
| 46778 | Zynq-7000 - How do I configure the PS DDRC board parameters? | N/A | N/A |
| 51790 | Zynq-7000 - 如何使用 DDRC 地址映射？ | N/A | N/A |
| 53039 | 14.3 EDK, Zynq-7000 DDRC - Why is the PS7 DDR Configuration limit DQS to Clock delay to -.100ns/0ns? | N/A | N/A |
| 51074 | 14.2 EDK, Zynq-7000 - 带 ECC 的 PS DDRC 不工作 | N/A | N/A |
| 47516 | Zynq-7000 SoC, DDR - 控制器误处理 STREX 指令 | N/A | N/A |
| 47484 | Zynq-7000 SoC、AXI — AXI_HP 访问 OCM 和 DDR 时，就会出现锁死 | N/A | N/A |
| 47514 | Zynq-7000 SoC、DDR — 在退出自刷新后，DDR3 启动 DRAM 时钟的时间过早 | N/A | N/A |
| 46723 | Zynq-7000 SoC – 我是否可以交换面向开发板设计的 PS DDR DQ 引脚？ | N/A | N/A |
| 60454 | 设计咨询 Zynq-7000 PS DDR 控制器 - DDR IO 在 ISE/EDK 和 Vivado 2013.3 及更早版本中配置不当 | N/A | N/A |
| 62042 | Zynq-7000 SoC, Vivado 2014.2 - PS DDRC asserts ODT during reads | N/A | N/A |
| AR# 53051 | |
|---|---|
| 日期 | 06/13/2018 |
| 状态 | Active |
| Type | 解决方案中心 |
| 器件 | |