The Zynq-7000 IBIS models are available on Xilinx.com under Device Models -> IBIS Models -> Zynq-7000 SoC -> Zynq-7000 IBIS Model:
https://www.xilinx.com/support/download.html
The following IBIS models should be used for DDRC simulation.
Note: While the labels may differ from Vivado/PlanAhead output, the underlying model should alias to the same model:
Address/Command Signals
DDR3:
SSTL15_S_PSDDR (1.5V) / SSTL135_S_PSDDR (1.35V)
DDR2:
SSTL18_I_S_PSDDR
LPDDR2:
HSUL_12_DCI40_S_PSDDR
(Note: This input model assumes a 40 Ohm DCI Reference.)
Note: The DDR_DRST_B signal does NOT use the LVCMOS IOSTANDARD as the soft MIG controller uses it.
Data and Clock Signals
DDR3:
Input: SSTL15_T_DCI_F_PSDDR_IN40_I (1.5V) / SSTL135_T_DCI_F_PSDDR_IN40_I (1.35V)
(Note: This input model assumes a 40 Ohm DCI Reference.)
Output: SSTL15_T_DCI_F_PSDDR_O (1.5V) / SSTL135_DCI_F_PSDDR_O (1.35V)
DDR2:
Input: SSTL18_II_DCI_F_PSDDR_IN50_I
(Note: This input model assumes a 50 Ohm DCI Reference.)
Output: SSTL18_II_DCI_F_PSDDR_O
LPDDR2:
HSUL_12_DCI40_F_PSDDR
(Note: This input model assumes a 40 Ohm DCI Reference.)
Other PS I/O, including MIO, should use one of the high-range (HR) based I/O models, depending on the bit field settings of the individual MIO pin MIO_PIN_xx registers: IO_Type and Speed (Slow or Fast edge rate).
For details on how to use the IBIS models and package files, see (Xilinx Answer 21632).
Starting with Vivado 2014.3, the "write_ibis" command can be used to write design-specific IBIS models for Zynq.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 52540 | Zynq-7000 SoC - Frequently Asked Questions | N/A | N/A |
| 53051 | Zynq-7000 SoC - PS DDR Controller | N/A | N/A |