This Release Notes and Known Issues Answer Record is for the Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express, released in ISE Design Suite 11.4, and contains the following information:
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
General Information
Important Note about Versions and Patches
ISE 11.5 contains an updated version of the ISE 11.4 v1.4 wrapper files.
When generated, these wrapper files are versioned as v1.4 rev 2, and this is noted in the readme that is generated with the wrapper files.
This wrapper was updated to fix the MMCM VCO settings issue for v1.4 discussed in (Xilinx Answer 34144)
The v1.4 rev 1 wrapper is a patch that enabled VHDL generation of the wrapper files when using ISE 11.4 v1.4 wrapper. See (Xilinx Answer 34182) for more information.
If you want to enable VHDL generation for the ISE 11.5 v1.4 rev 2 core, you will need to apply the v1.4 rev 3 patch from (Xilinx Answer 34611)
This patch is to be applied on top of ISE 11.5 and updates the VHDL wrapper file's MMCM VCO settings.
Full VHDL support was not natively available in ISE 11.4 which is why these patches are necessary to enable VHDL.
If you are not using VHDL then you do not need these patches.
The Virtex-6 FPGA Integrated Block Wrapper for PCI Express is shipped with a free license.
See (Xilinx Answer 33386) for more information.
The v1.4 integrated wrapper is targeted for Virtex-6 Production Silicon.
Users of CES (Engineering Sample) silicon must use the v1.3 integrated wrapper core.
Please see (Xilinx Answer 34033) for more information.
New Features
Resolved Issues
CR510476: VHDL source code generation support added.
VHDL source code generation is now supported. Also, includes Example Design, testbench and simulation, and implementation scripts.
CR518631: trn_rnp_ok_n is now supported in the 8-lane Gen2 Integrated Block.
Use of trn_rnp_ok_n is now supported in the 8-lane Gen 2 Integrated Block for PCI Express product.
CR528519: Use of TX-Phase Alignment circuit is enabled in GTX wrapper.
Use of TX-Phase Alignment circuit is now enabled in the GTX wrapper.
This enables adjustment of phase difference between XCLK and TXUSRCLK when the TX Buffer is bypassed and also adjusts TXUSRCLK to compensate for temperature / voltage variations in the global clock tree.
CR531739: Implementation support for the 8-lane Gen2 product with 256 Bytes Max.
Implementation support is now available for the 8-lane Gen 2 product with 256 Bytes Max Payload Size Configuration, in -2 speed grade devices.
CR531981: Implementation support for the 8-lane Gen2 product with 512 Bytes Max Payload Size Configuration, for 6VLX365T, in -3 speedgrade.
Implementation support is now available for the 8-lane Gen 2 product with 512 Bytes Max Payload Size Configuration, for 6VLX365T, in -3 speed grade.
CR533217: LTSSM state Recovery transition failure resolved.
Issue resolved where LTSSM state transition from Recovery.ReceiverLock to Recovery.ReceiverConfig could fail due to Lane-to-lane skew
CR526616: IBUFDS location when targeting ML605 Xilinx Development Board.
Issue resolved where the IBUFDS location used when targeting ML605 Xilinx Development Board was incorrect.
Known Issues
Virtex-6 FPGA solutions are pending hardware validation.
(Xilinx Answer 32934) -Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - How to enable 100 MHz reference clock for GEN 2 operation
(Xilinx Answer 33127) -Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - UCF constraint for sys_clk incorrect for ML605
(Xilinx Answer 33834) - Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Use of Component Name "core" Causes Implementation Failures using VHDL Flow
(Xilinx Answer 33835) - Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Area Group Constraints to Assist in x8 GEN 2 Timing Closure
(Xilinx Answer 33836) - Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Cannot Generate x8 GEN 2 Core for LX130T device using -2 speedgrade
(Xilinx Answer 33837) - Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - x8 GEN2 Operation is Not Supported in Virtex-6 HXT Devices for the v1.4 Release
(Xilinx Answer 33918) - Virtex-6, Spartan-6 FPGA and Block Plus Integrated Block Wrappers for PCI Express- Why is the root port model and testbench provided with the example simulation not passing Memory or I/O transactions to the user side interface?
(Xilinx Answer 33946) - Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Missing UCF constraint for x1, x2, and x4 Gen1 designs with a User Interface Clock of 250 MHz
(Xilinx Answer 34009)- Virtex-6 FPGA ML605 Board PCI Express Link Will Not Train; Implementations for PCI Express Must Use the v1.3 Integrated Block Wrapper for PCI Express
(Xilinx Answer 34033)- Virtex-6 FPGA Integrated Block Wrapper for PCI Express - The v1.4 core might fail to train reliably in Engineering Sample silicon
(Xilinx Answer 34182)- Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Patch to Enable VHDL File Generation
(Xilinx Answer 34144) - Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Incorrect MMCM VCO settings result in "ERROR:PhysDesignRules:1995 - The computed value for the VCO operating frequency..."
(Xilinx Answer 34280) - Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Gen 1 Training Fails with 100 MHz reference clock
(Xilinx Answer 34115) - Endpoint Block Plus Wrapper v1.4 for PCI Express - WARNING:Xst:2016 - Found a loop when searching source
(Xilinx Answer 34407) - Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Correct GTX settings for Transceiver Termination
(Xilinx Answer 35225) - Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Addresses read out from the BRAM are incorrect with the 128 Bit VHDL Wrapper.
v1.4 rev2 Known Issues
(Xilinx Answer 34611) - Virtex-6 FPGA Integrated Block Wrapper v1.4 rev 2 for PCI Express - Patch to Enable VHDL File Generation for v1.4 rev 2 released in ISE 11.5
(Xilinx Answer 34612) - Virtex-6 FPGA Integrated Endpoint Block v1.4 for PCI Express - Simulation failure when using ISE 11.5 to simulate a v1.4 core generated in ISE Design Suite 11.4
(Xilinx Answer 35426) -Virtex-6 FPGA Integrated Block for PCI Express - The v1.3, v1.3 rev 1,v1.4, and v1.4 rev 2wrapper might not link train on startup when using ISE Design Suite 11.5 or later
Revision History
05/03/2010 - Added 35426
04/12/2010 - Added CR555118
03/23/2010 - Added34115and34407
03/08/2010 - Updated to add 34611, 34612, notes about ISE 11.5 v1.4 rev2
02/22/2010 - Updated title for 32934
02/02/2010 - Added 34280
01/28/2010 - Added 34144
01/20/2010 - Added 34182
01/11/2010 - Added 33127 and fixed spacing problems
12/22/2009 - Added 34009, 34033
12/11/2009 - Added 33946
12/09/2009 - Added 33918
12/02/2009 - Initial Release
| AR# 33763 | |
|---|---|
| 日期 | 03/27/2015 |
| 状态 | Active |
| Type | 版本说明 |
| 器件 | |
| Tools | |
| IP | |