AR# 34280: Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Gen 1 Training Fails with 100 MHz reference clock
AR# 34280
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Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Gen 1 Training Fails with 100 MHz reference clock
描述
Gen 1 link training with 100 MHz reference clock might be sporadic due to problems in the MGT synchronization file (gtx_tx_sync_rate_v6.v[hd]).
解决方案
An update is available in (Xilinx Answer 34279). Download the zip file titled "ar34279_v6_pcie_v1_4.zip" from this Answer Record.
This ZIP file contains a file called"gtx_tx_sync_rate_v6.v[hd]" which contains updated synchronization logic. Place this file in your generated core's source directory.
Note that this ZIP file is cumulative and might contain fixes for other problems, as described in(Xilinx Answer 34279).