AR# 34407

描述

When generating Virtex-6 FPGA Integrated Block Wrapper for PCI Express,the following transceiver parameters are set in the GTX wrapper.

.TERMINATION_CTRL(5'b10101),
.TERMINATION_OVRD("TRUE"),

Are these the correct values?

解决方案

The following transceiver parameters are required for ES silicon:

.TERMINATION_CTRL(5'b10101),
.TERMINATION_OVRD("TRUE"),

For production silicon these values should be modified in the file /source/gtx_wrapper_v6.v as follows:

.TERMINATION_CTRL(5'b00000),
.TERMINATION_OVRD("FALSE"),

This will be fixed in the v1.5 release included in ISE software 12.1.

Revision History

03/23/2010 - Initial Release