AR# 56274

描述

How do I properly constrain the Video IP in my design?

The Product Guide contains some example constraints but they do not cover the cross clock domain paths in the associated Video IP.

解决方案

The following are some example constraints that show how to properly constrain the Video IP in Vivado 2013.2 design tools. 

Starting with Vivado 2013.3, these constraints are provided in the XDC constraints file included with the core.

• The following are recommended to cover all cross clock logic AND to avoid incorrectly constrained BUFGMUXs in the system with multiple clock inputs:

set video_clk [get_clocks -of [get_ports aclk]]

set axilite_clk [get_clocks -of [get_ports s_axi_aclk]] 

set_max_delay -from $video_clk -to [all_registers -clock $axilite_clk] -datapath_only [expr min([join [get_property PERIOD $video_clk] ,])]

set_max_delay -from $axilite_clk -to [all_registers -clock $video_clk] -datapath_only [expr min([join [get_property PERIOD $axilite_clk] ,])]

Note: The constraints should not be applied to Video IP core instances with the AXI4-Lite clock (s_axi_aclk) and Video clock (aclk) connected to the same clock source. 

The constraints should also not be applied to Video IP core instances with the AXI4-Lite interface disabled.

Also, refer to the Vivado Design Suite User Guide: Design Analysis and Closure Techniques for more information.
http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/design_tools.html

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