14.4/2012.4 Resolved Issue
(Xilinx Answer 52782)- ChipScope IBERT crashes when reprogramming with "Clean previous project setting" selected.
(Xilinx Answer 52142)- Vivado 14.3 - BSCAN channel set by user when implementation/synthesis runs resets selection.
(Xilinx Answer 53199)- 14.3 IBERT - RX Margin analysis uses incorrect scan range when testing multiple line rates
(Xilinx Answer 53202)-14.2 IBERT - Cannot perform RX Margin analysis on certain channels
(Xilinx Answer 53212)-ChipScope AXI Monitor - AXI Stream TDATA Width Must Be 32
(Xilinx Answer 53238)-14.2 Chipscope - Configuration fails in ChipScope when running on multiple machines
14.4/2012.4 Known Issues
(Xilinx Answer 52364)- ChipScope/iMPACT - Configuring a Virtex-7 XC7VH580T device with a bitstream generated in BitGen 14.2 causes the tool to crash.
(Xilinx Answer 53140)- ChipScopeIBERT reports different reference clock selections depending on if the line rate entry contains a decimal.
(Xilinx Answer 53166)-ChipScope IBERT GTH V7 does not enable DFE by default
(Xilinx Answer 52181)- MIG 7 Series - Critical warnings are generated when ChipScope cores are used in the Vivado tool
(Xilinx Answer 52233)- MIG 7 Series - The Vivado tool fails in GUI mode when debug signals are enabled
(Xilinx Answer 47680)- ChipScope Pro ILA - TRIG_OUT may give multiple pulses in 'Single' Trigger Run Mode.
14.3/2012.3 Resolved Issue
(Xilinx Answer 50728) - 2012.2 Vivado Debug - Warning is issued when re-opening implemented design with ILA 2.0 core
(Xilinx Answer 50724) - ChipScope Pro - An error occurs when configuring with a partial bitstream in ChipScope analyzer
(Xilinx Answer 50725) - ChipScope Pro Analyzer - I inserted an ILA 2.0 core in the Vivado tool, but ChipScope analyzer recognizes it as an unsupported core
(Xilinx Answer 51642) - ChipScope IBERT Artix - 14.2 Displays Different Line Rate than what was specified
(Xilinx Answer 51374) - ChipScope IBERT, Kintex-7 - Why am I unable to set a 0.5 Gb/s line rate in IBERT for a Kintex-7 device?
(Xilinx Answer 50646) - ChipScope IBERT, GTX IBERT - Using the proper GTX settings when targeting production silicon
(Xilinx Answer 50658) - ChipScope IBERT, 7 Series GTP IBERT - Issuing a QUAD reset in IBERT might cause other transceivers to lose link status
(Xilinx Answer 50628) - 7 Series GTX IBERT - An error occurs when sourcing from a Tcl file to create a project for defense grade devices
14.3/2012.3 Known Issues
(Xilinx Answer 52364) - ChipScope/iMPACT - Configuring a Virtex-7 XC7VH580T with a bistream generated in BitGen 14.2 causes the tool to crash
(Xilinx Answer 52139) - ChipScope IBERT, 14.3 - What version of IBERT should I use with Initial ES GTH?
(Xilinx Answer 52141) - ChipScope IBERT, 14.3 - What version of IBERT should I use with General ES GTH?
(Xilinx Answer 52142) - Vivado 14.3 - BSCAN channel set by user when implementation/synthesis runs resets selection
(Xilinx Answer 52181) - MIG 7 Series - Critical warnings are generated when ChipScope cores are used in the Vivado tool
(Xilinx Answer 52233) - MIG 7 Series - The Vivado tool fails in GUI mode when debug signals are enabled
14.2/2012.2 Resolved Issue
(Xilinx Answer 46426) - ChipScope Pro - Inserting ChipScope cores in PlanAhead tool generates unconnected ports
(Xilinx Answer 47094) - ChipScope - "ERROR:HDLCompiler:1318 - when generating ILA for 7 series XQ
(Xilinx Answer 47677) - ChipScope core might fail timing when using trigger width of greater than 256 and depth of more than 32K
(Xilinx Answer 47679) - ChipScope Pro ILA - ILA example design will not pass implementation on XC7Z045 device
(Xilinx Answer 47682) - ChipScope Analyzer - When editing the XADC registers in Analyzer, register 0x53 is missing a description
(Xilinx Answer 46859) - 7 Series GTH IBERT core in ISE Design Suite14.1 only supports the 690T device
(Xilinx Answer 46768) - Spartan-6 GTP IBERT - The line rate shows an incorrect rate when running at 2.5 Gb/s
(Xilinx Answer 47390) - ChipScope IBERT - 7 series GTH IBERT core bitstream uses generic bitstream name
(Xilinx Answer 47681) - ChipScope IBERT - SuperClock-2 BCS description for SP623, ML623 and all 72X boards is not clear
(Xilinx Answer 45648) - Virtex-7, Kintex-7 - Using KC705 or VC707 "Board Configuration Setting" in GTX IBERT uses incorrect I/O Standard for system clock
14.2/2012.2 Known Issues
(Xilinx Answer 47680) - ChipScope Pro ILA - TRIG_OUT may give multiple pulses in 'Single' Trigger Run Mode.
(Xilinx Answer 43903) - ChipScope - Core Inserter Freezes after going to ILA Parameters Page due to "java.lang.OutOfMemoryError" Error
(Xilinx Answer 42856) - ChipScope Pro Analyzer - "Clean Previous Project Settings" applies to all devices in JTAG chain
(Xilinx Answer 44190) - ChipScope Pro - ATC2 Core - CRITICAL WARNING: Could not resolve non-primitive black box cell 'OPAD'
(Xilinx Answer 45218)- ChipScope Analyzer - Net names not getting properly imported when CDC and bit files are located in a directory with spaces
(Xilinx Answer 50583) -2012.2/14.2 - ChipScope Pro - 7-Series GTX IBERT, 1.X ILA, ICON, VIO cores support Zynq-7000 devices
(Xilinx Answer 50725) -14.2:ChipScope Pro Analyzer - I inserted a ILA 2.0 core in Vivado but ChipScope Analyzer recognizes it as an unsupported core
(Xilinx Answer 50728) -2012.2 Vivado Debug - Warning is issued when re-opening implemented design with ILA 2.0 core
(Xilinx Answer 47095)- ChipScope Pro Analyzer 13.3/13.4 - Kintex-7 CSE internal error partial reconfiguration
(Xilinx Answer 44664)- Virtex-5 GTP - 1 Gb/s line rate does not work when targeting a Virtex-5 LX20T device
(Xilinx Answer 44624)- Virtex-5, GTP/GTX IBERT CORE Generator - IBERT Sweep Test of PREEMPHASIS Does Not Work
(Xilinx Answer 45381)- ChipScope GTX IBERT, Virtex-5 FXT/TXT - Performing a sweep test on DFETAP values does not work correctly
(Xilinx Answer 50628) -2012.2 Vivado - 7-Series GTX IBERT - When sourcing from a tcl file to create a project for defense grade devices, an error occurs
(Xilinx Answer 50646) -14.2, 7 Series GTX IBERT - Using the proper GTX settings when targeting production silicon
(Xilinx Answer 50658) -14.2, 7 Series GTP IBERT - Issuing a QUAD reset in IBERT may cause other transceivers to lose link status
14.1 Known Issues
(Xilinx Answer 46426) - ChipScope Pro - Inserting ChipScope cores in PlanAhead tool generates unconnected ports
(Xilinx Answer 47094) - ChipScope - "ERROR:HDLCompiler:1318 - when generating ILA for 7 series XQ
(Xilinx Answer 47095) - ChipScope Pro Analyzer 13.3/13.4 - Kintex-7 CSE internal error partial reconfiguration
(Xilinx Answer 47677) - ChipScope core might fail timing when using trigger width of greater than 256 and depth of more than 32K
(Xilinx Answer 47679) - ChipScope Pro ILA - ILA example design will not pass implementation on XC7Z045 device
(Xilinx Answer 47680) - ChipScope Pro ILA - TRIG_OUT may give multiple pulses in 'Single' Trigger Run Mode.
(Xilinx Answer 47682) - ChipScope Analyzer - When editing the XADC registers in Analyzer, register 0x53 is missing a description
(Xilinx Answer 43903) - ChipScope - Core Inserter Freezes after going to ILA Parameters Page due to "java.lang.OutOfMemoryError" Error
(Xilinx Answer 42856) - ChipScope Pro Analyzer - "Clean Previous Project Settings" applies to all devices in JTAG chain
(Xilinx Answer 44190) - ChipScope Pro - ATC2 Core - CRITICAL WARNING: Could not resolve non-primitive black box cell 'OPAD'
(Xilinx Answer 45218) - ChipScope Analyzer - Net names not getting properly imported when CDC and bit files are located in a directory with spaces
(Xilinx Answer 46859) - 7 Series GTH IBERT core in ISE Design Suite14.1 only supports the 690T device
(Xilinx Answer 46768) - Spartan-6 GTP IBERT - The line rate shows an incorrect rate when running at 2.5 Gb/s
(Xilinx Answer 47390) - ChipScope IBERT - 7 series GTH IBERT core bitstream uses generic bitstream name
(Xilinx Answer 47681) - ChipScope IBERT - SuperClock-2 BCS description for SP623, ML623 and all 72X boards is not clear
(Xilinx Answer 44664) - Virtex-5 GTP - 1 Gb/s line rate does not work when targeting a Virtex-5 LX20T device
(Xilinx Answer 44624) - Virtex-5, GTP/GTX IBERT CORE Generator - IBERT Sweep Test of PREEMPHASIS Does Not Work
(Xilinx Answer 45381) - ChipScope GTX IBERT, Virtex-5 FXT/TXT - Performing a sweep test on DFETAP values does not work correctly
(Xilinx Answer 45648) - Virtex-7, Kintex-7 - Using KC705 or VC707 "Board Configuration Setting" in GTX IBERT uses incorrect I/O Standard for system clock
Revision History:
05/08/2012 - Initial Release for 14.1
07/25/2012 - Updated for 14.2/2012.2 Known Issues
10/12/2012 - Updated for 14.3/2012.3 Known Issues and Resolved Issues