AR# 35157

描述

• New Features
• Resolved Issues
• Known Issues

解决方案

• ISE 12.1 design tools support
• Designed to RapidIO Interconnect Specification v2.1
• Virtex-6 LXT/HXT/SXT 5.0 Gb/s device support
• Spartan-6 3.125 Gb/s and 4x device support
• Expanded simulator support
• Support for ML505, ML605 and SP605 boards (Xilinx Answer 29159)

• PHY does not properly pass CRF bit to Buffer (CR# 519603)
• GT settings for Spartan-6 and Virtex-6 FPGA updated based on characterization
• Processing Element Features CAR implemented incorrectly. Part of the PEF CAR was implemented in the PHY configuration space, now it is merged into the LOGIO configuration space as directed by the spec. See core User Guide for map of configuration space.
• (Xilinx Answer 34490) Port_initialized intermittently toggles
  (Xilinx Answer 33574) Recommended modifications to Example Design reset scheme
• (Xilinx Answer 33527) Example design "implement.bat" file has error
• (Xilinx Answer 32195) Virtex-4 FXT 3.125G, 4x core might not meet timing

• (Xilinx Answer 33528) ISE GUI does not recognize certain core constraints
• (Xilinx Answer 30023) Core cannot train down to x1 mode if lane 0 is disconnected
• (Xilinx Answer 29522) Problem running Synplify flow with Serial RapidIO core
• (Xilinx Answer 24982) Restart-from-Retry followed by Link Request causes illegal Packet Not Accepted cause
• (Xilinx Answer 24970) Control symbol might be lost when reinitialization is forced
• (Xilinx Answer 24968) Logical Layer Receive side cannot handle stalls on incoming Rx packets, data corruptions might be seen
• (Xilinx Answer 35182) VIO Example Design removed from certain configurations
• (Xilinx Answer 35187) Getting Started Guide lists inaccurate location of instantiation templates
• (Xilinx Answer 35796) Why can't a Buffer Depth of 32 be selected when targeting a CXT device?
• (Xilinx Answer 36342) Example reset module might fail to completely reset the buffer
• (Xilinx Answer 35570) Port_initialized fails to assert in Virtex-6 Core
• (Xilinx Answer 37912) Core receives unexpected Packet Not Accepted control symbols
• (Xilinx Answer 39795) Corrupt packets reach the user interface
• (Xilinx Answer 53260) - The core sends only one LREQ when 'Additional Link Requests Before Fatal' parameter is set to '1', instead of two
• (Xilinx Answer 53261) - LREQ-IS is not sent if the core receives PR and PNA at the same time

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