The ChipScope cores can be removed or added to the design based on the value of the VIO_SRIO parameter (Verilog) or generic (VHDL) set in the "< component_name >_top.v(hd)" file. When set to '0', the ChipScope cores are not included in the design, when set to '1', the ChipScope cores are added to the design.
To add the ChipScope cores back in to the design for these configurations, change the setting from '0' to '1'.