The Virtex-6 DDR2/DDR3 Design requires specific board layout rules be followed in order for the design to behave correctly in hardware. The following Answer Records provide detailed information on the board layout requirements. Information can also be found in the DDR2 and DDR3 Memory Interface Solution > Design Guidelines section of The Virtex-6 Memory Interface Solutions User Guide.
On top of following these rules, it is strongly recommended users run SI Simulations using IBIS Models to verify signal integrity:
If after verifying these rules have been followed and errors are still seen in hardware, please refer back to the main Hardware section of this Design Assistant to look into Pin-out/Banking Requirements and Hardware Debug.
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
34557 | MIG Virtex-6 and 7 Series DDR3 - Fly-by Topology Requirements | N/A | N/A |
34569 | MIG - Simultaneously Switching Noise (SSN) Calculation | N/A | N/A |
Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
---|---|---|---|
35193 | MIG Virtex-6 DDR2/DDR3 - Debugging Read Leveling Stage 2 | N/A | N/A |
35183 | MIG Virtex-6 DDR2/DDR3 - Debugging Read Leveling Stage 1 | N/A | N/A |
34709 | MIG Virtex-6 DDR2/DDR3 - Debugging Data Errors | N/A | N/A |
34708 | MIG Virtex-6 DDR2/DDR3 - SI Simulation using IBIS | N/A | N/A |
34589 | MIG Virtex-6 DDR2/DDR3 - General Board Level Debug | N/A | N/A |
34556 | MIG Virtex-6 DDR2/DDR3 - Termination and I/O Standard Guidelines | N/A | N/A |
34286 | MIG Design Assistant - Virtex-6 DDR2/DDR3 Hardware | N/A | N/A |
34743 | MIG Virtex-6 DDR2/DDR3 - Debugging Calibration Failures | N/A | N/A |
34558 | MIG Virtex-6 DDR2/DDR3 - Trace Matching Guidelines | N/A | N/A |