AR# 34743

描述

The PHY logic contains state logic for initializing the SDRAM memory after power-up and performs timing training of the read and write data paths to account for system static and dynamic delays. Successful completion of this calibration process is denoted by the assertion of phy_init_done. When phy_init_done does not assert, there are various design aspects that must be analyzed. This section of the MIG Design Assistant focuses on the proper debug process for root causing calibration failures (phy_init_done does not assert).

NOTE: This Answer Record is contained in a series of MIG hardware debug Answer Records and assumes you are running the MIG Example Design with the Debug Port Enabled. It is best to start at the beginning of this recommended hardware debug flow; see (Xilinx Answer 34588).

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

• Changes to the output MIG UCF/Pin-Out, RTL, Parameters.
• Board related issues such as not adhering to the Memory Implemenation Guidelines specified for the MIG design.
• Not running SI Simulations using IBIS models.

The first steps in any calibration debug is to:

• Verify Pin-Out and Banking MIG Requirements have been followed; see (Xilinx Answer 34308).
• Verify Board-Layout Requirements have been followed (includes SI Simulation information); see (Xilinx Answer 34544).

• For general information on the different calibration stages, see (Xilinx Answer 34740).
• For information on determining the calibration stage that caused phy_init_done to not assert (signifying a calibration failure), see (Xilinx Answer 35169).

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