AR# 35129

描述

Read Leveling Stage 2 is a stage performed by the Virtex-6 MIG DDR3/DDR2 PHY during initial calibration.The purpose of the stage is to align the captured data word in the resynchronization clock domain.This calibration stage is performed in simultaneously with Write Calibration (DDR3 Only).

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

• Accounts for skew between different DQS Groups (Each DQSGroup must be within 3 clock cycles from the other DQS Groups)
• Determines the time between when a read command is issued to the PHY and when the corresponding read data is returned to the controller

Additional Information:

• For detailed information on Read Leveling Stage 2, please see the DDR2/DDR3 SDRAM Memory Interface Solution > Core Architecture > PHY section in UG406.
• For information on debugging calibration errors/failures, please see (Xilinx Answer 34743).
• For more information on the resynchronization clock, please see (Xilinx Answer 34540).
• For more information on the full series of calibration steps, please see (Xilinx Answer 34740).

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