2. 技术支持
  3. AR# 3470: 12.1 Constraints - How do I LOC a PAD to an edge, multiple sites, or banks?
  4. AR# 34708: MIG Virtex-6 DDR2/DDR3 - SI Simulation using IBIS

AR# 34708

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MIG Virtex-6 DDR2/DDR3 - SI Simulation using IBIS

描述

A critical step in verifying board layout guidelines for memory interface designs have been followed is to run signal integrity simulations using IBIS. These simulations should always be run both pre-board layout and post-board layout. The purpose of running these simulations is to confirm the signal integrity on the board.

NOTE: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

The ML561 Hardware-Simulation Correlation chapter of the Virtex-5 FPGA ML561 Memory Interfaces Development Board User Guide can be used as a guideline. This chapter provides a detailed look at signal integrity correlation results for the ML561 board, and can be used as an example for what to look at and what you should see. It also provides steps to create a design-specific IBIS model to aid in setting up the simulations.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
40775 MIG Spartan-6 MCB - Board Layout N/A N/A
34544 MIG Virtex-6 DDR2/DDR3 - Board Layout N/A N/A
AR# 34708
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
IP
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