This section of the MIG Design Assistant focuses on Supported Features for Virtex-6 DDR3/DDR2 designs. Below you will find information related to your specific question.
NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.
For a complete list of supported features and frequency support for Virtex-6 FPGA DDR3/DDR2 designs, refer to the "DDR3 SDRAM Features" and "DDR2 SDRAM Features" sections in the Virtex-6 FPGA Memory Interface Solutions Data Sheet (DS186): http://www.xilinx.com/support/documentation/ip_documentation/ds186.pdf
The following links provide additional information regarding specific features:
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 41495 | MIG Virtex-6 DDR2/DDR3 - Design information on ECC | N/A | N/A |
| 34415 | MIG Virtex-6 DDR2/DDR3 - Data Widths | N/A | N/A |
| 34330 | MIG Virtex-6 DDR2/DDR3 - JEDEC Specification | N/A | N/A |
| 34327 | MIG Virtex-6 DDR2/DDR3/QDRII+ - Multi-Controllers | N/A | N/A |
| 34322 | MIG 7 Series and Virtex-6 DDR2/DDR3 - MIG Options | N/A | N/A |
| 34283 | MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation | N/A | N/A |
| 34266 | Xilinx Virtex-6 MIG Solution Center - Design Assistant | N/A | N/A |
| 34314 | MIG 7 系列和 Virtex-6 DDR2/DDR3 - 器件支持 | N/A | N/A |
| 34282 | MIG Design Assistant - Virtex-6 Core Functionality | N/A | N/A |
| 34324 | MIG Virtex-6 DDR2/DDR3 - Rank Support | N/A | N/A |