AR# 34330

描述

This section of the MIG Design Assistant focuses on the JEDEC Specification as it applies to the MIG Virtex-6 DDR3/DDR2 FPGA designs. Below you will find information related to your specific question.

NOTE: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

The MIG Virtex-6 DDR2/DDR3 controller completes a JEDEC standard compliant initialization sequence. The simulation testbench skips the initial 200 s delay to speed up simulation times. In hardware, this requirement is observed.The controller adheres to all timing parameters as defined by the JEDEC standards.

The following links provide additional detail regarding the MIG controller and various requirements regarding the JEDEC standards:

• (Xilinx Answer 34355) - DDR3 ZQ Calibration
• (Xilinx Answer 35094) - DDR3 Write Leveling
• (Xilinx Answer 34359) - DDR3 Multi-Purpose Register
• (Xilinx Answer 34370) - DDR3 Reset
• (Xilinx Answer 34371) - Auto Refresh Counter
• (Xilinx Answer 34396) - Self-Refresh
• (Xilinx Answer 34397) - Additive Latency
• (Xilinx Answer 38685)- Power Down Mode

链接问答记录

主要问答记录

相关答复记录