This is the Release Note Answer Record for the Soft Error Mitigation Controller (SEM IP) for UltraScale FPGA and newer device families.
*** Important Note for SEM IP Designs ***
Beginning with the Vivado 2015.3 release, the SEM IP Product Guide contains an appendix containing the IP Design Checklist.
To aid with integrating SEM IP into a design, review the IP Design Checklist and ensure all recommendations are adhered to:
(PG187) UltraScale Architecture Soft Error Mitigation Controller
Xilinx Forums:
Please seek technical support via the UltraScale Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
Version Information:
| Vivado Version | IP Version |
| Vivado 2015.1 | v2.0 rev2 |
| Vivado 2015.3 | v3.0 rev0 |
| Vivado 2015.4 | v3.0 rev1 |
| Vivado 2016.1 | v3.1 rev0 |
| Vivado 2016.2 | v3.1 rev1 |
| Vivado 2016.3 | v3.1 rev2 |
| Vivado 2017.1 | v3.1 rev3 |
| Vivado 2017.2 | v3.1 rev4 |
| Vivado 2017.3 | v3.1 rev5 |
| Vivado 2017.4 | v3.1 rev6 |
| Vivado 2018.1 | v3.1 rev7 |
| Vivado 2018.2 | v3.1 rev8 |
| Vivado 2018.3 | v3.1 rev9 |
| Vivado 2018.3.1 | v3.1 rev10 |
| Vivado 2019.1 | v3.1 rev11 |
| Vivado 2019.2 | v3.1 rev12 |
| Vivado 2019.2.1 | v3.1 rev13 |
| Vivado 2020.1 | v3.1 rev14 |
| Vivado 2020.2 | v3.1 rev15 |
| Vivado 2021.1 | v3.1 rev16 |
Supported Devices:
UltraScale FPGA:
The SEM IP supports all UltraScale FPGAs except the XCKU025. The XCKU025 has a reduced set of configuration features. Please refer to (DS890) and (UG570) for more information.
For the supported devices, SEM IP is a Production IP as of Vivado 2016.1.
UltraScale+ FPGA, Zynq UltraScale+ MPSoC, and Zynq UltraScale+ RFSoC devices:
| Device | IP Status | Remark |
| XCKU3P | Production | |
| XCKU5P | Production | |
| XCKU9P | Production | |
| XCKU11P | Production | |
| XCKU13P | Production | |
| XCKU15P | Production | |
| XCVU3P | Production | |
| XCVU5P | Production | |
| XCVU7P | Production | |
| XCVU9P | Production | |
| XCVU11P | Production | |
| XCVU13P | Production | |
| XCVU19P | Production | |
| XCVU15P | Production | |
| XCVU23P | Production | |
| XCVU27P | Production | |
| XCVU29P | Production | |
| XCVU31P | Production | |
| XCVU33P | Production | |
| XCVU35P | Production | |
| XCVU37P | Production | |
| XCVU45P | Production | |
| XCVU47P | Production | |
| XCVU57P | Production | |
| XCZU2 | Production | |
| XCZU3 | Production | |
| XCZU4 | Production | |
| XCZU5 | Production | |
| XCZU6 | Production | |
| XCZU7 | Production | |
| XCZU9 | Production | |
| XCZU11 | Production | |
| XCZU15 | Production | |
| XCZU17 | Production | |
| XCZU19 | Production | |
| XCZU21DR | Production | |
| XCZU25DR | Production | |
| XCZU27DR | Production | |
| XCZU28DR | Production | |
| XCZU29DR | Production | |
| XCZU39DR | Production | |
| XCZU46DR | Production | |
| XCZU47DR | Production | |
| XCZU48DR | Production | |
| XCZU49DR | Production | |
| XCU25 | Production | |
| XCU30 | Production | |
| XCU50 | Production | |
| XCU200 | Production | |
| XCU250 | Production | |
| XCU280 | Production | |
| u55n | Production | |
| u55c | Production | |
| xck26 | Production | |
| xcux35 | Production |
*This table will be updated for each Vivado tools release, and lists the presently supported device under the most recent version.
**Contact Xilinx Technical Support for more information.
General Guidance
| Answer Record | Title | Applicable Version |
| (Xilinx Answer 70684) | UltraScale+ - SEM IP - How to use the SEM IP error report to look up essential bit error locations using the essential bit data (EBD) file | |
| (Xilinx Answer 69888) | Soft Error Mitigation (SEM) IP - UltraScale+ Status Heartbeat Gap | |
| (Xilinx Answer 69889) | Soft Error Mitigation (SEM) IP UltraScale+ design fails SPI flash timing | |
| (Xilinx Answer 69652) | Soft Error Mitigation IP - Mode pins should not be set to 101 for UltraScale/+ SSI devices | |
| (Xilinx Answer 69417) | 2017.1 write_bitstream - Partial Reconfiguration bitstream is potentially incorrect which may affect device readback | |
| (Xilinx Answer 68978) | Soft Error Mitigation (SEM) IP - Using UltraScale+ SEM IP in Vivado IP Integrator | 2017.1 |
| (Xilinx Answer 67939) | Soft Error Mitigation IP - Location of the makedata.tcl file changed since 2016.3 | 2016.3 |
| (Xilinx Answer 67178) | Soft Error Mitigation (SEM) IP UltraScale and UltraScale+ Bitstream Encryption and Authentication | 2017.3 |
| (Xilinx Answer 66570) | UltraScale Architecture Soft Error Mitigation Controller - Guidance for testing with error injection | 2015.3 |
| (Xilinx Answer 67086) | UltraScale - SEM IP - How to use the SEM IP error report to look up bit error locations using essential bit data in the EBD file? | |
| (Xilinx Answer 67128) | SEM support limitations for UltraScale+ ES1 devices | |
| (Xilinx Answer 67180) | Can SEM support clock frequencies lower than 8 MHz? | |
| (Xilinx Answer 67041) | Soft Error Mitigation (SEM) IP - Using UltraScale SEM IP in Vivado IP Integrator | |
| (Xilinx Answer 65402) | Soft Error Mitigation (SEM) IP - Increased interface errors when performing error injection into configuration memory | 2015.1 |
| (Xilinx Answer 64512) | UltraScale SEM v2.0 device and feature support guidance for 2015.1 | 2015.1 |
| (Xilinx Answer 65550) | Soft Error Mitigation (SEM) IP SSI timing closure might not be met without pin LOCs | 2015.1 |
| (Xilinx Answer 65551) | UltraScale Soft Error Mitigation (SEM) IP XCVU440 makedata.tcl only supports monolithic die SPI flash devices | 2016.1 |
| (Xilinx Answer 67041) | Soft Error Mitigation (SEM) IP - Using UltraScale SEM IP in Vivado IP Integrator | 2016.1 |
| (Xilinx Answer 72238) | Zynq UltraScale+ MPSoC - Vivado Readback Verify fails when PL SYSMON is configured via APB Slave Interface | |
| (Xilinx Answer 73057) | UltraScale+ Soft Error Mitigation Controller (PG187) Updates for v3.1 rev 12 release | 2019.2 |
| (Xilinx Answer 73243) | UltraScale+ Soft Error Mitigation Controller (PG187) Updates for v3.1 rev 13 release | 2019.2.1 |
| (Xilinx Answer 75933) | UltraScale+ Soft Error Mitigation Controller – (PG187) Updates for v3.1 rev 15 release | 2020.2 |
| (Xilinx Answer 76638) | UltraScale+ Soft Error Mitigation Controller – (PG187) Updates for v3.1 rev 16 release | 2021.1 |
Known Issues
| Answer Record | Title | Version Found | Version Resolved |
| (Xilinx Answer 71155) | Soft Error Mitigation IP - VU35P and VU37P reported error locations and address translations might be incorrect | 2018.2 | 2018.3 |
| (Xilinx Answer 71153) | Soft Error Mitigation IP - VU37P has incorrect constraint for Frame ECC | 2018.1 | 2018.2 |
| (Xilinx Answer 70487) | Soft Error Mitigation IP - Kintex UltraScale KU085 SEM IP will not boot up properly | 2017.4 | 2018.1 |
| (Xilinx Answer 70683) | Soft Error Mitigation IP - Example top RTL fetch_rxdata bit width is incorrect | 2017.4 | 2018.1 |
| (Xilinx Answer 68940) | Soft Error Mitigation (SEM) IP UltraScale+ Architecture SSI devices do not assert all of the status_* signals during halt condition (HLT) | 2017.1 | 2017.2 |
| (Xilinx Answer 68939) | Soft Error Mitigation (SEM) IP UltraScale+ Architecture SSI VU11P and VU13P Halts during initialization. | 2017.1 | 2017.2 |
| (Xilinx Answer 68977) | Soft Error Mitigation (SEM) IP UltraScale+ Architecture VU13P (SSI) Querying frames in SLR 3 does not work | 2017.1 | 2017.2 |
| (Xilinx Answer 68938) | Soft Error Mitigation (SEM) IP UltraScale+ Architecture SSI VU13P [Timing 38-282] Negative SETUP slack violation | 2017.1 | 2017.3 |
| (Xilinx Answer 64513) | UltraScale SEM v2.0 Query by LFA command does not work for SSI devices | 2015.1 | 2015.3 |
| (Xilinx Answer 65552) | UltraScale Soft Error Mitigation (SEM) IP XCVU190 classification makedata.tcl is incorrect | 2015.3 | 2015.4 |
| (Xilinx Answer 66906) | Soft Error Mitigation (SEM) IP [DRC 23-20] Rule violation (PDCN-1569) LUT equation term check | 2016.1 | 2016.3 |
| (Xilinx Answer 66905) | Soft Error Mitigation (SEM) IP SSI device status_heartbeat timing violation | 2016.1 | 2016.3 |
| (Xilinx Answer 71314) | Guidance and Mitigation for Configuration Readback induced Time Interval Error in MMCMs and PLLs | NA | NA |
Note: the "version found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.