(Xilinx Answer 53245) Vivado: a netlist generated for timing simulation looks to be the UNISIM-based netlist
(Xilinx Answer 62566) 2014.x - Sim Models - VHDL - Inverted std_ulogic parameters changed to bit - Which models changed?
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Xilinx Answer 62183) cascaded DSP48E2 slices report DRC warning in simulation: [Unisim DSP48E2-7], why?
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Xilinx Answer 60984) 2013.4/2014.1/2014.2 Vivado Simulation - PCIE_3_ 1 - VCS VHDL simulation reports Error Type mismatch 'SIM_JTAG_IDCODE' is STD_LOGIC_VECTOR, but formal 'SIM_JTAG_IDCODE' is INTEGER
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Xilinx Answer 42133) IODELAY - Why is there an insertion delay even when tap is set to 0 in behavioral simulation?