AR# 60984

描述

When using VCS to simulate PCIE 3_1 generated in the Vivado IP catalog, the following error can occur:

Error-[OVA1ACTUALTYPEMISMATCH_COMPONENT_ENTITY] Type mismatch
 
$XILINX_VIVADO/data/vhdl/src/unisims/secureip/PCIE_3_1.vhd, 1312
 
SIP_PCIE_3_1
 
  Line 1.794:
 
  Please generate .lis file by 'vhdlan -list ...' and see details.
 
 --+       GSR => GSR)
 
  Actual 'SIM_JTAG_IDCODE' is STD_LOGIC_VECTOR, but formal 'SIM_JTAG_IDCODE'  is INTEGER when binding component
 

  'SIP_PCIE_3_1'($XILINX_VIVADO/data/vhdl/src/unisims/secureip/PCIE_3_1.vhd:1310)

  to entity

  'SIP_PCIE_3_1'($XILINX_VIVADO/data/secureip/pcie_3_1/pcie_3_1_001.vp:16).Instance
 
  label is
 
  'PCIE_3_1_INST'($XILINX_VIVADO/data/vhdl/src/unisims/secureip/PCIE_3_1.vhd:6835).

解决方案

This issue is fixed in Vivado 2014.3. 

Workaround:

1. Use VCS version I-2014.03.

2. Open the file PCIE_3_1.vhd from the location: $XILINX_VIVADO\data\vhdl\src\unisims\secureip and go to line 576.

SIM_JTAG_IDCODE : std_logic_vector(31 downto 0) := X"00000000";

SIM_JTAG_IDCODE : std_logic_vector(31 downto 0) := X"00000000";

SIM_JTAG_IDCODE : bit_vector(31 downto 0) := X"00000000";

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