In 7 Series/Virtex-6/Spartan-6 IODELAY behavioral simulation, there is an insertion delay even when the tap is set to 0.
What is this delay?
Why is it seen in behavioral simulation?
This delay models the IODELAY intrinsic component delay, which is the amount of delay through the IODELAY even with tap=0.
This delay is a behavioral model so that users do not overlook the real insertion delay.
Normally, delays are not modeled in behavioral simulation, but the delay block is an exception because users expect the behavior to be the same as in real hardware, for example, intrinsic delay plus tap delay.
This delay was added to the model for the Virtex-6, Spartan-6, and newer architectures and not for older architectures.
The following table outlines the delay value in each device family.
| Device | Input Side Delay | Output Side Delay |
|---|---|---|
| 7-series | IDELAYE2 = 600 ps | ODELAYE2 = 600 ps |
| Virtex-6 | IODELAYE1 = 144 ps | IODELAYE1 = 144 ps |
| Spartan-6 | IODELAY2 = 100 ps | IODELAY2 = no initial delay modeled |
| Virtex-5 | IODELAY = no initial delay modeled | IODELAY = no initial delay modeled |
| Virtex-4 | IDELAY = no initial delay modeled | No output delay available |