AR# 40519

Serial RapidIO v5.6 - Release Notes and Known Issues for ISE Design Suite 13.1

描述

This Release Notes and Known Issues Answer Record is for the Serial RapidIO v5.6 Core, which was released in ISE 13.1 Design Suite and contains the following information:

Supported Devices
New Features
Resolved Issues
Known Issues

For installation instructions, general CORE Generator known issues, and design tool requirements, see the IP Release Notes Guide:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

解决方案

Supported Devices

Virtex-4 XC FX
Virtex-5 XC LXT/SXT/TXT/FXT
Virtex-6 XC CXT/LXT/SXT/HXT
Spartan-6 XC LXT

New Features

ISE 13.1 Design Suite support

Resolved Issues

(Xilinx Answer 35570) PORT_INITIALIZED fails to assert in Virtex-6 1.25 G and 2.5 G cores (CR 576404)
(Xilinx Answer 36342) Example design reset module fails to completely reset the buffer (CR 566276)
(Xilinx Answer 38132) Virtex-6 MMCM BANDWIDTH attribute incorrect (CR 574172)
PHY ignores LREQ received while PHY is issuing a PNA (CR 579364)
PHY sometimes issues PR in addition to LRESP after receiving LREQ (CR 575534)
(Xilinx Answer 39795) PHY passes corrupted received packets on to buffer interface (CR 580844)
(Xilinx Answer 37912) PHY inserts idle sequences before EOP on some transmitted packets (CR 574885)

Known Issues

(Xilinx Answer 33528) NGDBuild errors when using ISE GUI unless XST Keep Hierarchy set to Soft (CR 534514)
(Xilinx Answer 32396) Generating a core through Project Navigator causes example files to be overwritten (CR 578001)
(Xilinx Answer 32195) Virtex-4 FX 3.125G, 4x core might not meet timing (CR 506364)
(Xilinx Answer 30023) Unable to traindown to x1 mode in Lane 2 (CR 457109)
(Xilinx Answer 30021) Core reinitialization during error recovery causes recoverable protocol (CR 457885)
(Xilinx Answer 29522) Post-Synplicity synthesis implementation runs may exhibit ucf failures (CR 447782)
(Xilinx Answer 24982) PNA cause field may occasionally reflect a reserved value (CR 436767)
(Xilinx Answer 24970) Control Symbols may be lost on reinit (CR 436768)
(Xilinx Answer 24968) Logical Rx does not support core side stalls (CR 436770)
(Xilinx Answer 51958) - ERROR:ConstraintSystem:59 - Constraint <NET "phy_4x_ser_clk/UCLK_DV4" TNM_NET = "UCLK_DV4";> [xiltest_srio_v5_6_top.ucf(94)]: NET "phy_4x_ser_clk/UCLK_DV4"
(Xilinx Answer 53260) - The core sends only one LREQ when 'Additional Link Requests Before Fatal' parameter is set to '1', instead of two
(Xilinx Answer 53261) - LREQ-IS is not sent if the core receives PR and PNA at the same time

Revision History:

02/17/2011 - Initial Release
03/01/2011 - Updated for 13.1
09/26/2012 - Added (Xilinx Answer 51958)
12/03/2012 - Added (Xilinx Answer 53260) and (Xilinx Answer 53261)

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链接问答记录

子答复记录

Answer Number	问答标题	问题版本	已解决问题的版本
35570	Serial RapidIO v5.5 - Port_initialized fails to assert in Virtex-6 FPGA Core	N/A	N/A
32195	Serial RapidIO v5.2, v5.3 - Virtex-4 FX 3.125G, 4x core might not meet timing	N/A	N/A
29522	LogiCORE RapidIO - Problem running Synplify flow with Serial RapidIO core	N/A	N/A
24968	LogiCORE RapidIO - Logical Layer Receive side cannot handle stalls on incoming Rx packets, data corruptions might be seen	N/A	N/A
39795	Serial RapidIO v5.5 - Corrupt packets reach the user interface	N/A	N/A
37912	Serial RapidIO v5.5 - Core receives unexpected "Packet Not Accepted" control symbols	N/A	N/A
51958	Serial RapidIO v5.6：ERROR:ConstraintSystem:59 - Constraint <NET ''phy_4x_ser_clk/UCLK_DV4'' TNM_NET = ''UCLK_DV4'';> [xiltest_srio_v5_6_top.ucf(94)]: NET ''phy_4x_ser_clk/UCLK_DV4''	N/A	N/A

相关答复记录

Answer Number	问答标题	问题版本	已解决问题的版本
38132	Virtex-6 FPGA MMCM 设计咨询 - MMCM BANDWIDTH 属性要求	N/A	N/A
35570	Serial RapidIO v5.5 - Port_initialized fails to assert in Virtex-6 FPGA Core	N/A	N/A
32195	Serial RapidIO v5.2, v5.3 - Virtex-4 FX 3.125G, 4x core might not meet timing	N/A	N/A
29522	LogiCORE RapidIO - Problem running Synplify flow with Serial RapidIO core	N/A	N/A
24968	LogiCORE RapidIO - Logical Layer Receive side cannot handle stalls on incoming Rx packets, data corruptions might be seen	N/A	N/A
39795	Serial RapidIO v5.5 - Corrupt packets reach the user interface	N/A	N/A
37912	Serial RapidIO v5.5 - Core receives unexpected "Packet Not Accepted" control symbols	N/A	N/A
34396	MIG 7 Series and Virtex-6 DDR2/DDR3 - JEDEC Specification Self-Refresh	N/A	N/A

AR# 40519
日期	12/03/2012
状态	Active
Type	版本说明
器件	Spartan-6 LXT Virtex-5 FXT Virtex-5 LXT Virtex-5 SXT Virtex-5 TXT Virtex-6 CXT Virtex-6 HXT Virtex-6 LXT Virtex-6 SXT Virtex-4 FX More Less
Tools	ISE Design Suite - 13.1
IP	Serial RapidIO

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