This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP Color Filter Array Interpolation Core.
The following information is listed for each version of the core:
Color Filter Array Interpolation LogiCORE IP Page:
| (Xilinx Answer 34068) | What algorithm does the Xilinx Color Filter Array Interpolation use? |
| (Xilinx Answer 36149) | When using the transparent or constant modes, does h_blank need to be asserted when v_blank is asserted? |
| (Xilinx Answer 34828) | How do I simulate my Video IP pCore in EDK? |
| (Xilinx Answer 51589) | Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
| (Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
| (Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
| (Xilinx Answer 51589) | Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
| (Xilinx Answer 47455) | Why does the CFA fail if the image size is less than 128x128 pixels? |
| (Xilinx Answer 41725) | Why is the output wrong when I select a 12-bit data path for the netlist and the C-Model? |
| (Xilinx Answer 41589) | Does the CFA affect the original Bayer pattern input data? |
| (Xilinx Answer 54069) | Why does the CFA fail to generate if the maximum number of columns or rows is set to larger than 1024 when using the EDK pCore in XPS? |
| (Xilinx Answer 41589) | Does the CFA affect the original Bayer pattern input data? |
| (Xilinx Answer 41725) | Why is the output wrong when I select a 12-bit data path for the netlist and the C-Model? |
| (Xilinx Answer 54069) | Why does the CFA fail to generate if the maximum number of columns or rows is set to larger than 1024 when using the EDK pCore in XPS? |
| (Xilinx Answer 33872) | "ERROR:simAn IP generation script exited abnormally. Error found during generation." |
| (Xilinx Answer 37987) | Where can I find UG762: Xilinx Streaming Video Interface User Guide? |
| (Xilinx Answer 38830) | Why are some of the detected values one less than expected? |
| (Xilinx Answer 38912) | Why is VBLANK and HBLANK polarity wrong for the Constant Interface? |
| (Xilinx Answer 32340) | Why does my Image Pipe Video IP core fail to update the netlist when the parameters or the license is changed, but the component name remains constant? |
| (Xilinx Answer 33581) | Why is the output simulation netlist for my design encrypted, and only readable by the ISE tools simulator? |
| (Xilinx Answer 33872) | "ERROR:sim An IP generation script exited abnormally. Error found during generation." |
| (Xilinx Answer 35130) | Why do I get the following error when generating with a Design Linking License? ERROR:sim Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380The design contains secured core. |
| AR# 32133 | |
|---|---|
| 日期 | 07/17/2018 |
| 状态 | Archive |
| Type | 版本说明 |
| IP | |