Packaging an RTL Block as Vivado IP

RTL Kernels must be packaged as a Vivado® IP suitable for use in IP integrator. See Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118) for details on IP packaging in Vivado.

The following interface packaging is required for the RTL Kernel:

• The AXI4-Lite interface name must be packaged as S_AXI_CONTROL, but the underlying AXI ports can be named differently.
• The AXI4 MM interfaces must be packaged as AXI4 master endpoints with 64 bit address support.
  • Xilinx strongly recommends that AXI4 MM interfaces be packaged with AXI meta data HAS_BURST=0 and SUPPORTS_NARROW_BURST=0. These properties can be set in an IP level bd.tcl file. This indicates wrap and fixed burst type is not used and narrow (sub-size burst) is not used.
• ap_clk and ap_clk_2 must be packaged as clock interfaces.
• ap_rst_n and ap_rst_n_2 must be packaged as active low reset interfaces.
• ap_clk must be packaged to be associated with all AXI4-Lite, AXI4 MM, and AXI4-Stream interfaces.

To test if the RTL kernel is packaged correctly for IP integrator, try to instantiate the packaged kernel in IP integrator. In the GUI it should show up as having interfaces for clock, reset, AXI4-Lite slave, AXI4 MM master, and AXI4-Slave only. No other ports should be present in the canvas view. The properties of the AXI interface can be viewed by selecting the interface on the canvas. Then in the Block Interface Properties window, select the Properties tab and expand the CONFIG table entry. If an interface is to be read-only or write-only then the unused AXI channels can be removed and the READ_WRITE_MODE will be set to read-only or write-only.