Two Dimensional Read and Write

Below is the code snippet from the Row of 2D Array Using AXI4-Master Interface in “kernel_to_gmem” category on Xilinx On-boarding Example GitHub that shows the recommended coding style for inferring burst read and write of two dimensional arrays. Note that the data from the global memory inx is read consecutively into the local memory buffer_in in the inner loop. Also note that the inner loop is pipelined using the xcl_pipeline_loop attribute.

#define NUM_ROWS   64
#define WORD_PER_ROW 64

void read_data(__global int* inx, int* buffer_in) 
{
    for(int i = 0; i < NUM_ROWS; ++i) {
        __attribute__((xcl_pipeline_loop))
        for (int j = 0; j < WORD_PER_ROW; ++j) {
            buffer_in[WORD_PER_ROW*i+j] = inx[WORD_PER_ROW*i+j];
        }
    }
}

The Device Hardware Transaction view below shows that the burst read and write requests are sent out from the kernel as indicated by the Read Address and Write Address channels. It also shows that the read and write data are transferred continuously between the kernel and the global memory after the requests have been serviced.