For applications requiring very high bandwidth to the global memory, devices with multiple DDR
banks can be targeted so that kernels can access all available memory banks simultaneously. For
example, SDAccel™ includes platforms that support multiple DDR banks.
In order to take advantage of multiple DDR banks, users need to assign CL memory buffers to
different banks in the host code as well as configure XCL binary file to match the bank
assignment in xocc command line.
The block diagram shows the “Global Memory Two Banks Example” in “kernel_to_gmem” category on Xilinx On-boarding Example GitHub that connects the input pointer to DDR
bank 0 and output pointer to DDR bank 1.
