The SDAccel™ Environment includes a variety of FPGA
acceleration cards with different DDR memory configurations. The following figure shows the
data path between a kernel and one of four DDR channels on the XIL-ACCEL-RD-KU115 card. Each
DDR channel provides 20GB/s of raw DDR bandwidth with 80GB/s total for the entire card.
Figure: Data Path Between a Kernel and an XIL-ACCEL-RD-KU115 Card
The width of the data path between the kernel and the memory
interconnect/controller can configured by the SDAccel compiler as 32, 64,
128, 256, and 512 bits depending on the kernel argument types. For applications that require
maximum data bandwidth between the kernel and DDR memory, it is recommended that global
pointers are defined explicitly as 512-bit data types.
