Download Vivado® ML Standard Edition free. Purchase licensing options for Enterprise Edition start at $2995.
Vivado ML Edition Features | Vivado ML Standard Edition | Vivado ML Enterprise Edition | Vivado Lab Edition |
---|---|---|---|
Licensing Option | Free | 30-day Evaluation - Free On Demand on AWS Marketplace NL: $2995 FL: $3595 |
|
Device Support | Limited Xilinx Devices | All Xilinx Devices | |
Vivado IP Integrator | |||
Dynamic Function eXchange | |||
Vitis High-Level Synthesis | |||
Vivado Simulator | |||
Vivado Device Programmer | |||
Vivado Logic Analyzer | |||
Vivado Serial I/O Analyzer | |||
Debug IP (ILA/VIO/IBERT) | |||
Synthesis and Place and Route | |||
Vitis Model Composer | Buy NL - $500 FL - $700 |
Buy NL - $500 FL - $700 |
The following tables provide the typical and peak Vivado memory usage per target device. Xilinx recommends to have have at minimum enough physical system memory to handle the peak memory usage.
Notes:
Windows / Linux (64-bit) | ||
Device | Typical | Peak |
All devices* | 20 | 32 |
Windows / Linux (64-bit) | ||
Device | Typical | Peak |
XCKU3P | 7 | 13 |
XCKU5P | 7 | 13 |
XCKU9P | 8 | 13 |
XCKU11P | 9 | 13 |
XCKU13P | 10 | 14 |
XCKU15P | 10 | 15 |
Windows / Linux (64-bit) | ||
Device | Typical | Peak |
XCVU3P | 11 | 19 |
XCVU5P | 12 | 19 |
XCVU7P | 15 | 24 |
XCVU9P | 20 | 32 |
XCVU11P | 22 | 32 |
XCVU13P | 28 | 47 |
XCVU19P | 48 | 64 |
Windows / Linux (64-bit) | ||
Device | Typical | Peak |
XCZU2EG | 3 | 5 |
XCZU3EG | 4 | 6 |
XCZU4EV | 5 | 8 |
XCZU5EV | 6 | 9 |
XCZU6EG | 7 | 10 |
XCZU7EV | 8 | 11 |
XCZU9EG | 10 | 14 |
XCZU11EG | 11 | 18 |
XCZU15EG | 11 | 18 |
XCZU17EG | 12 | 18 |
XCZU19EG | 14 | 21 |
Windows / Linux (64-bit) | ||
Device | Typical | Peak |
XCZU21DR | 10 | 14 |
XCZU25DR | 11 | 14 |
XCZU27DR | 13 | 17 |
XCZU28DR | 14 | 17 |
XCZU29DR | 14 | 17 |
Windows / Linux (64-bit) | ||
Device | Typical | Peak |
XCKU025 | 5 | 7 |
XCKU035 | 5 | 7 |
XCKU040 | 5 | 7 |
XCKU060 | 7 | 11 |
XCKU085 | 9 | 14 |
XCKU095 | 9 | 14 |
XCKU115 | 9 | 14 |
Windows / Linux (64-bit) | ||
Device | Typical | Peak |
XCVU065 | 7 | 11 |
XCVU080 | 8 | 12 |
XCVU095 | 9 | 14 |
XCVU125 | 10 | 16 |
XCVU160 | 14 | 20 |
XCVU190 | 18 | 24 |
XCVU440 | 32 | 48 |
Windows / Linux (64-bit) | ||
Device | Typical | Peak |
XC7V585T | 4 | 6 |
XC7V2000T | 10 | 16 |
XC7VX330T | 3 | 5 |
XC7VX415T | 3 | 5 |
XC7VX485T | 4 | 5 |
XC7VX550T | 4 | 6 |
XC7VX690T | 5 | 7 |
XC7VX980T | 7 | 9 |
XC7VX1140T | 8 | 10 |
XC7VH580T | 4 | 6 |
XC7VH870T | 6 | 8 |
Windows / Linux (64-bit) | ||
Device | Typical | Peak |
XC7K70T | 1.6 | 2.5 |
XC7K160T | 2 | 3 |
XC7K325T | 3 | 4 |
XC7K355T | 3 | 5 |
XC7K410T | 3 | 5 |
XC7K420T | 3 | 5 |
XC7K480T | 4 | 6.5 |
Windows / Linux (64-bit) | ||
Device | Typical | Peak |
XC7A15T | 2 | 3 |
XC7A35T | 2 | 3 |
XC7A50T | 2 | 3 |
XC7A75T | 2 | 3 |
XC7A100T | 2 | 3 |
XC7A200T | 2.5 | 3.5 |
Windows / Linux (64-bit) | ||
Device | Typical | Peak |
XC7Z010 | 1 | 1.6 |
XC7Z015 | 1.3 | 1.9 |
XC7Z020 | 1.3 | 1.9 |
XC7Z030 | 1.8 | 2.7 |
XC7Z035 | 3 | 5 |
XC7Z045 | 3 | 5 |
Xilinx® supports the following operating systems on x86 and x86-64 processor architectures.
Note: Please refer to PetaLinux Tools Documentation: Reference Guide (UG1144) for more information on Installation Requirements for supported Operating Systems with PetaLinux.
The following table lists architecture support for commercial products in Vivado™ ML Standard versus Vivado ML Enterprise edition. For non-commercial support all Xilinx automotive devices are supported in Vivado ML Standard Edition when available as production devices in the tools.
Device | Vivado ML Standard Edition | Vivado ML Enterprise Edition |
---|---|---|
Zynq® | Zynq-7000 SoC Device: • XC7Z010, XC7Z015, XC7Z020, XC7Z030, XC7Z007S, XC7Z012S, and XC7Z014S |
Zynq-7000 SoC Device: • All |
Zynq® UltraScale+™ MPSoC | UltraScale+ MPSoC: • XCZU2EG, XCZU2CG, XCZU3EG, XCZU3CG XCZU4EG, XCZU4CG, XCZU4EV, XCZU5EG, XCZU5CG, XCZU5EV, XCZU7EV, XCZU7EG, and XCZU7CG |
UltraScale+ MPSoC: • All |
Zynq UltraScale+ RFSoC | UltraScale+ RFSoC: • None |
UltraScale+ RFSoC: • All |
Alveo | Alveo: • All |
Alveo: • All |
Kria | Kria • All |
Kria: • All |
Versal | N/A | AI Core Series: • VC1902 • VC1802 Prime Series • VM1802 |
Virtex FPGA | Virtex-7 FPGA: Virtex UltraScale FPGA: |
Virtex-7 FPGA: Virtex UltraScale FPGA: Virtex UltraScale+ FPGA: Virtex UltraScale+ HBM: Virtex UltraScale+ 58G: |
Kintex FPGA | Kintex®-7 FPGA: Kintex UltraScale FPGA: Kintex UltraScale+ FPGA: |
Kintex®-7 FPGA: Kintex UltraScale FPGA: Kintex UltraScale+: |
Artix FPGA | Artix-7 FPGA: • XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T, XC7A100T, XC7A200T |
Artix-7 FPGA: • All |
Artix UltraScale+ | Artix UltraScale+ •XCAU25P •XCU20P |
Artix UltraScale+ • All |
Spartan-7 | Spartan-7: • XC7S6, XC7S15 • XC7S25, XC7S50• XC7S75, XC7S100 |
Spartan-7: • All |
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Access the below free Vivado training courses when you sign up for the Developer Program.
Video Title | Description |
---|---|
Introduction to FPGA Architecture, 3D ICs, SoCs | Overview of FPGA architecture, SSI technology, and SoC device architecture. |
UltraFast Design Methodology: Board and Device Planning | Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist. |
HDL Coding Techniques | Covers basic digital coding guidelines used in an FPGA design. |
Introduction to Vivado Design Flows | Introduces the Vivado design flows: the project flow and non-project batch flow. |
Vivado Design Suite Project-based Flow | Introduces the project-based flow in the Vivado Design Suite: creating a project, adding files to the project, exploring the Vivado IDE, and simulating the design. |
Behavioral Simulation | Describes the process of behavioral simulation and the simulation options available in the Vivado IDE. |
Vivado Synthesis and Implementation | Create timing constraints according to the design scenario and synthesize and implement the design. |
Vivado Design Suite I/O Pin Planning | Use the I/O Pin Planning layout to perform pin assignments in a design. |
Vivado IP Flow | Customize IP, instantiate IP, and verify the hierarchy of your design IP. |
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Video Title | Description |
---|---|
Designing FPGAs Using the Vivado Design Suite 1 | This training content offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design. |
Designing FPGAs Using the Vivado Design Suite 2 | This content builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course. Learn how to build a more effective FPGA design. |
Designing FPGAs Using the Vivado Design Suite 3 | This content builds further on the previous Designing FPGAs Using the Vivado Design Suite 1 & 2.Learn how to effectively employ timing closure techniques. |
Designing FPGAs Using the Vivado Design Suite 4 | Learn how to use the advanced aspects of the Vivado® Design Suite and Xilinx hardware. The focus is on applying timing constraints for source-synchronous and system-synchronous interfaces, utilizing floorplanning techniques, and more. |
Xilinx hands-on FPGA and Embedded Design training provides you the foundational knowledge necessary to begin designing right away. These programs target both engineers new to FPGA technology and experienced engineers developing complex connectivity, digital signal processing, or embedded solutions. Contact your local Sales Rep or Authorized Training Provider to see if your company has any Training Credits available. Learn more