2. 技术支持
  3. AR# 7053:
  4. AR# 70530: 2017.4 LogiCORE IP MIPI D-PHY v4.0 (rev.1) - Patch Updates for the MIPI D-PHY LogiCORE IP v4.0 (rev.1)

AR# 70530

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2017.4 LogiCORE IP MIPI D-PHY v4.0 (rev.1) - Patch Updates for the MIPI D-PHY LogiCORE IP v4.0 (rev.1)

描述

This answer record contains patch updates for the MIPI D-PHY LogiCORE IP v4.0 (rev.1).

解决方案

This patch fixes the following issue in the LogiCORE IP MIPI D-PHY 4.0 (rev.1) generated from the Vivado 2017.4 design tools.

  • Patch Rev1 - (Xilinx Answer 69274) - Why does the ulpsactivenot only assert for one clock period for the MIPI D-PHY RX?
  • Patch Rev1 - (Xilinx Answer 70581) - Why do I see SoT/ECC/CRC errors on MIPI RX IP targeting UltraScale+ devices?

See the individual Answer Record for details on which release the issue is fixed in.

Patch Installation:

Install the patch as per the instructions in the included README.txt file to resolve this issue.

附件

文件名 文件大小 File Type
AR70530_Vivado_2017_4_preliminary_rev1.zip 1 MB ZIP

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
54550 LogiCORE IP MIPI D-PHY - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
69274 LogiCORE IP MIPI D-PHY v3.1, v3.1 (Rev. 1) and v4.0 (Rev. 1) - Why does the ulpsactivenot only assert for one clock period for the MIPI D-PHY RX? N/A N/A
70581 LogiCORE IP MIPI D-PHY Controller v4.0 (rev.1) (or MIPI CSI-2 Receiver Subsystem v3.0 (Rev. 1)) - Why do I see SoT/ECC/CRC errors on MIPI RX IP targeting UltraScale+ devices? N/A N/A
AR# 70530
日期 04/24/2018
状态 Active
Type 综合文章
器件
Tools
IP
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